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authorBastian Ruppert <Bastian.Ruppert@Sewerin.de>2011-10-04 23:43:28 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-11-03 22:56:25 +0100
commitf9fc237f1f07d4e5ff7c9c2da39cabc8d3d7b339 (patch)
tree04672966185e65ec9a5a36c99313afcf3472db32 /board/davinci
parent4dd834906dcc8207f82a686e060ffaa7b7ac878f (diff)
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Davinci: ea20: set console on UART0
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'board/davinci')
-rw-r--r--board/davinci/ea20/ea20.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 9d0f71b..4e4107a 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -48,12 +48,12 @@ static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 5 }
};
-/* UART pin muxer settings */
+/* UART0 pin muxer settings */
static const struct pinmux_config uart_pins[] = {
- { pinmux(0), 4, 6 },
- { pinmux(0), 4, 7 },
- { pinmux(4), 2, 4 },
- { pinmux(4), 2, 5 }
+ { pinmux(3), 2, 7 },
+ { pinmux(3), 2, 6 },
+ { pinmux(3), 2, 4 },
+ { pinmux(3), 2, 5 }
};
#ifdef CONFIG_DRIVER_TI_EMAC
@@ -104,7 +104,7 @@ static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
{ DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_UART0 }, /* console */
{ DAVINCI_LPSC_GPIO },
};
@@ -150,7 +150,7 @@ int board_init(void)
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART2),
+ DAVINCI_SYSCFG_SUSPSRC_UART0),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
@@ -167,7 +167,7 @@ int board_init(void)
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart2_ctrl_regs->pwremu_mgmt);
+ &davinci_uart0_ctrl_regs->pwremu_mgmt);
return 0;
}