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authorStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
committerStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
commitf61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch)
treeab90f076f18e56b2b3e8c9375b95917daa78c1d9 /board/csb472
parentec081c2c190148b374e86a795fb6b1c49caeb549 (diff)
parentf82642e33899766892499b163e60560fbbf87773 (diff)
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/csb472')
-rw-r--r--board/csb472/init.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/csb472/init.S b/board/csb472/init.S
index aec42a1..4b6958a 100644
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -82,11 +82,11 @@ ext_bus_cntlr_init:
mflr r3 /* get address of ..getAddr */
/* Calculate number of cache lines for this function */
- addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+ addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
mtctr r4
..ebcloop:
icbt r0, r3 /* prefetch cache line for addr in r3*/
- addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+ addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
bdnz ..ebcloop /* continue for $CTR cache lines */
/********************************************************************