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| author | Wolfgang Denk <wd@denx.de> | 2009-09-30 23:26:59 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-09-30 23:26:59 +0200 |
| commit | 9ae7ae6b4dd9d0c6489ac5b054846f80cfd973b8 (patch) | |
| tree | d5b5c439fd49237040c81ba9fb733d1b90bf37ee /board/csb272/init.S | |
| parent | 7b5ae460c34fa43261fe1ded71dc9c33d3ffd8e5 (diff) | |
| parent | b306db2f1bf561b5823a655c677fe28cfad80cfb (diff) | |
| download | u-boot-imx-9ae7ae6b4dd9d0c6489ac5b054846f80cfd973b8.zip u-boot-imx-9ae7ae6b4dd9d0c6489ac5b054846f80cfd973b8.tar.gz u-boot-imx-9ae7ae6b4dd9d0c6489ac5b054846f80cfd973b8.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'board/csb272/init.S')
| -rw-r--r-- | board/csb272/init.S | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/csb272/init.S b/board/csb272/init.S index 15b26f8..a6b0d40 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -175,26 +175,26 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) + WDCR_SDRAM(SDRAM0_CFG, 0x00000000) /* * Configure Memory Banks */ - WDCR_SDRAM(mem_mb0cf, 0x00084001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) + WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) + WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) /* * Set up SDTR1 (SDRAM Timing Register) */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) + WDCR_SDRAM(SDRAM0_TR, 0x00854009) /* * Set RTR (Refresh Timing Register) */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + WDCR_SDRAM(SDRAM0_RTR, 0x10000000) + /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -210,7 +210,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) + WDCR_SDRAM(SDRAM0_CFG,0x80800000) ..sdri_done: blr /* Return to calling function */ |