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| author | wdenk <wdenk> | 2003-04-05 00:53:31 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-04-05 00:53:31 +0000 |
| commit | 3e38691e8f7aa0d9b498d76c7279ddec6e4946f3 (patch) | |
| tree | bec2e661298847dc5bcf9335ef31259686e882e1 /board/csb226 | |
| parent | 36c05a80ecbe3997abd9aa628a68dd6c0bacf681 (diff) | |
| download | u-boot-imx-3e38691e8f7aa0d9b498d76c7279ddec6e4946f3.zip u-boot-imx-3e38691e8f7aa0d9b498d76c7279ddec6e4946f3.tar.gz u-boot-imx-3e38691e8f7aa0d9b498d76c7279ddec6e4946f3.tar.bz2 | |
* Patch by Arun Dharankar, 4 Apr 2003:
Add IDMA example code (tested on 8260 only)
* Add support for Purple Board (MIPS64 5Kc)
* Add support for MIPS64 5Kc CPUs
* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
* Patch by Denis Peter, 04 Apr 2003:
- update MIP405-4 board
* Patches by Denis Peter, 03 April 2003:
- fix PCI IRQs on MPL boards
- fix two more un-relocated pointer problems
* Fix behaviour of "run" command:
- print error message iv variable does not exist
- terminate processing of arguments in case of error
* Patches by Peter Figuli, 10 Mar 2003
- Add support for BTUART on PXA platform
- Add support for WEP EP250 (PXA) board
* Fix flash problems on INCA-IP; add tool to allow bruning images to
flash using a BDI2000
* Implement fix for I2C Edge Conditions problem for all boards that
use the bit-banging driver (common/soft_i2c.c)
* Add patches by Robert Schwebel, 31 Mar 2003:
- csb226 board: bring in sync with innokom/memsetup.S
- csb226 board: fix MDREFR handling
- misc doc fixes / extensions
- innokom board: cleanup, MDREFR fix in memsetup.S, config update
- add BOOT_PROGRESS to armlinux.c
Diffstat (limited to 'board/csb226')
| -rw-r--r-- | board/csb226/memsetup.S | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/board/csb226/memsetup.S b/board/csb226/memsetup.S index 6567184..60f9d50 100644 --- a/board/csb226/memsetup.S +++ b/board/csb226/memsetup.S @@ -38,6 +38,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE sub pc,pc,#4 .endm +_TEXT_BASE: + .word TEXT_BASE + /* * Memory setup @@ -222,23 +225,28 @@ mem_init: /* Step 2c: Write FLYCNFG FIXME: what's that??? */ /* ---------------------------------------------------------------- */ + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ + adr r3, mem_init /* r0 <- current position of code */ + ldr r2, =mem_init + cmp r3, r2 /* skip init if in place */ + beq initirqs + /* ---------------------------------------------------------------- */ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ /* ---------------------------------------------------------------- */ /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DIR field. */ + /* this to power on defaults + DRI field. */ - ldr r4, =0x03ca4fff - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 - ldr r4, =0x03ca4030 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ + ldr r4, [r1, #MDREFR_OFFSET] /* ---------------------------------------------------------------- */ @@ -258,18 +266,16 @@ mem_init: /* Step 4: Initialize SDRAM */ /* ---------------------------------------------------------------- */ - /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ + /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] /* Step 4b: de-assert MDREFR:SLFRSH. */ - bic r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_SLFRSH) str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] |