diff options
| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /board/cray/L1/L1.c | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
| download | u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.zip u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.gz u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.bz2 | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'board/cray/L1/L1.c')
| -rw-r--r-- | board/cray/L1/L1.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index f0dfa07..1c82bdf 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -139,7 +139,7 @@ int misc_init_r (void) struct rtc_time tm; char bootcmd[32]; - hdr = (image_header_t *) (CFG_MONITOR_BASE - image_get_header_size ()); + hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ()); #if defined(CONFIG_FIT) if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { puts ("Non legacy image format not supported\n"); @@ -181,9 +181,9 @@ int rtc_get (struct rtc_time *tmp) { return 0; } -void rtc_set (struct rtc_time *tmp) +int rtc_set (struct rtc_time *tmp) { - return; + return 0; } void rtc_reset (void) { @@ -205,13 +205,13 @@ static void init_sdram (void) /* To set the appropriate timings, we need to know the SDRAM speed. */ /* We can use the PLB speed since the SDRAM speed is the same as */ /* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25Mhz. */ -/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */ -/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */ +/* 405GP reference clock, which on the L1 is 25MHz. */ +/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ +/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ -/* write SDRAM timing for 100Mhz. */ +/* write SDRAM timing for 100MHz. */ mtdcr (memcfga, mem_sdtr1); mtdcr (memcfgd, 0x0086400D); |