Merge branch 'master' of /home/stefan/git/u-boot/u-boot

4 files changed, 50 insertions, 50 deletions

diff --git a/board/cpu87/config.mk b/board/cpu87/config.mk
index 6384c78..6a694a4 100644
--- a/board/cpu87/config.mk
+++ b/board/cpu87/config.mk
@@ -25,7 +25,7 @@
 # CPU87 board
 #
 
-# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in configs/cpu87.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
index c7a96f9..057a34c 100644
--- a/board/cpu87/cpu87.c
+++ b/board/cpu87/cpu87.c
@@ -227,7 +227,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = &memctl->memc_psdmr;
@@ -252,7 +252,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -263,7 +263,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -277,45 +277,45 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9, size10;
 #endif
 	long psize;
 
 	psize = 32 * 1024 * 1024;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
-	size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	psize = max(size8,max(size9,size10));
 
 	if (psize == size8) {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	} else if (psize == size9){
-		psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:9COL) ");
 	} else
 		printf ("(60x:10COL) ");
 
-#endif	/* CFG_RAMBOOT */
+#endif	/* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -325,7 +325,7 @@ phys_size_t initdram (int board_type)
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
 
diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h
index 5dbd4ae..45cb853 100644
--- a/board/cpu87/cpu87.h
+++ b/board/cpu87/cpu87.h
@@ -6,19 +6,19 @@
 #define REG8(x)			(*(volatile unsigned char *)(x))
 
 /* CPU86 register definitions */
-#define CPU86_VME_EAC		REG8(CFG_BCRS_BASE + 0x00)
-#define CPU86_VME_SAC		REG8(CFG_BCRS_BASE + 0x01)
-#define CPU86_VME_MAC		REG8(CFG_BCRS_BASE + 0x02)
-#define CPU86_BCR		REG8(CFG_BCRS_BASE + 0x03)
-#define CPU86_BSR		REG8(CFG_BCRS_BASE + 0x04)
-#define CPU86_WDOG_RPORT	REG8(CFG_BCRS_BASE + 0x05)
-#define CPU86_MBOX_IRQ		REG8(CFG_BCRS_BASE + 0x04)
-#define CPU86_REV		REG8(CFG_BCRS_BASE + 0x07)
-#define CPU86_VME_IRQMASK	REG8(CFG_BCRS_BASE + 0x80)
-#define CPU86_VME_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x81)
-#define CPU86_LOCAL_IRQMASK	REG8(CFG_BCRS_BASE + 0x82)
-#define CPU86_LOCAL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x83)
-#define CPU86_PMCL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x84)
+#define CPU86_VME_EAC		REG8(CONFIG_SYS_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CONFIG_SYS_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CONFIG_SYS_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CONFIG_SYS_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CONFIG_SYS_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CONFIG_SYS_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x84)
 
 /* Board Control Register bits */
 #define CPU86_BCR_FWPT		0x01
diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c
index f7e121f..c35757b 100644
--- a/board/cpu87/flash.c
+++ b/board/cpu87/flash.c
@@ -28,7 +28,7 @@
 #include <mpc8xx.h>
 #include "cpu87.h"
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
@@ -183,7 +183,7 @@ unsigned long flash_init (void)
 
 	/* Init: no FLASHes known
 	 */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -192,8 +192,8 @@ unsigned long flash_init (void)
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
-	size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+	size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
 
 	if (size_b0 > 0 || size_b1 > 0) {
 
@@ -216,22 +216,22 @@ unsigned long flash_init (void)
 	/* protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
 	if (size_b1) {
-		/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+		/* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
 		 * but we shouldn't protect it.
 		 */
 
 		flash_protect  (FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
 		);
 	}
 #else
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
 	);
 #endif
 #endif
@@ -240,7 +240,7 @@ unsigned long flash_init (void)
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
 # endif
-# if CONFIG_ENV_ADDR >= CFG_BOOTROM_BASE
+# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
 	if (size_b1) {
 		flash_protect (FLAG_PROTECT_SET,
 				CONFIG_ENV_ADDR,
@@ -391,7 +391,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		last  = start;
 		addr = (vu_char *)(info->start[l_sect]);
 		while ((addr[0] & 0x80) != 0x80) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				return 1;
 			}
@@ -443,7 +443,7 @@ AMD_DONE:
 				last = start;
 				while ((addr[0] & 0x00800080) != 0x00800080 ||
 				   (addr[1] & 0x00800080) != 0x00800080) {
-					if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+					if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 						printf ("Timeout (erase suspended!)\n");
 						/* Suspend erase
 						 */
@@ -558,7 +558,7 @@ static int write_word (flash_info_t * info, volatile unsigned long *addr,
 
 	start = get_timer (0);
 	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			/* Suspend program
 			 */
 			*addr = 0x00B000B0;
@@ -613,7 +613,7 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}