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| author | Robby Cai <R63905@freescale.com> | 2011-02-18 14:55:10 +0800 |
|---|---|---|
| committer | Robby Cai <R63905@freescale.com> | 2011-04-16 14:09:05 +0800 |
| commit | 6d20b6a7428e51a0b2abcbaf291287bcb38aba63 (patch) | |
| tree | 1546b15dd6818d60d312d2a623adc0f8c607bc5d /board/cpu87/cpu87.h | |
| parent | 9576d798ae1f6e3d67992553875159703b2eea93 (diff) | |
| download | u-boot-imx-6d20b6a7428e51a0b2abcbaf291287bcb38aba63.zip u-boot-imx-6d20b6a7428e51a0b2abcbaf291287bcb38aba63.tar.gz u-boot-imx-6d20b6a7428e51a0b2abcbaf291287bcb38aba63.tar.bz2 | |
ENGR00142246 MX50 Update DDR2 script to use more optimized settings
New DDR2 initialization script from designer includes
controller changes as well as very important PHY changes that increase
internal sampling window to detect DQS edge. This increase
compensates for possible jitter.
The script, Codex_DDR2_266MHz.inc v3, is found at
http://compass.freescale.net/livelink/
livelink?func=ll&objId=218722501&objAction=browse&viewType=1
Also corrected the DDR clock. (DDR mode changed from Sync to Async)
Signed-off-by: Robby Cai <R63905@freescale.com>
Diffstat (limited to 'board/cpu87/cpu87.h')
0 files changed, 0 insertions, 0 deletions