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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/cpu86/cpu86.h | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/cpu86/cpu86.h')
| -rw-r--r-- | board/cpu86/cpu86.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h index cf7852c..ca0c39f 100644 --- a/board/cpu86/cpu86.h +++ b/board/cpu86/cpu86.h @@ -6,19 +6,19 @@ #define REG8(x) (*(volatile unsigned char *)(x)) /* CPU86 register definitions */ -#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) -#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) -#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) -#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) -#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) -#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) -#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) -#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) -#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) -#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) -#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) +#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00) +#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01) +#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02) +#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03) +#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04) +#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05) +#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04) +#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07) +#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80) +#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81) +#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82) +#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83) +#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84) /* Board Control Register bits */ #define CPU86_BCR_FWPT 0x01 |