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author | Stefan Roese <sr@denx.de> | 2016-03-16 08:48:21 +0100 |
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committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:27 +0800 |
commit | 82ceba2ca2487c4967419cf7053e1301709219e5 (patch) | |
tree | 8579f7dd51e295c0e18696d6f38084129bf47a98 /board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c | |
parent | 374e78efb0c6739c8c700325acca769d7a9e47de (diff) | |
download | u-boot-imx-82ceba2ca2487c4967419cf7053e1301709219e5.zip u-boot-imx-82ceba2ca2487c4967419cf7053e1301709219e5.tar.gz u-boot-imx-82ceba2ca2487c4967419cf7053e1301709219e5.tar.bz2 |
x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).
Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.
Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe
Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c')
-rw-r--r-- | board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c new file mode 100644 index 0000000..6a946d5 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <winbond_w83627.h> +#include <asm/gpio.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> + +int board_early_init_f(void) +{ + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the Winbond one can be used. + */ + setup_internal_uart(0); + + /* Enable the legacy UART in the Winbond W83627 Super IO chip */ + winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), + UART0_BASE, UART0_IRQ); + + return 0; +} + +int arch_early_init_r(void) +{ + return 0; +} |