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authorStephen Warren <swarren@nvidia.com>2012-01-06 12:14:42 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-02-12 10:11:22 +0100
commit2996e2dcc0454207b4bf6248d034aead4ac54591 (patch)
tree485fc935723d55e624d72d53cf85179f7d9f118f /board/compal/paz00
parent9057e652c30d8b2f4d9f3613a3923bd191843487 (diff)
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tegra2: Add support for Compal Paz00 (Toshiba AC100)
The Toshiba AC100 (Compal code-name Paz00, aka Dynabook AZ) is a netbook derived from the NVIDIA Tegra Harmony reference board. It ships with Android, but is often repurposed to run Linux. This patch adds just enough support to get a U-Boot serial console, and the ability access built-in eMMC and the external SD slot. v2: * Rebased on latest HEAD, incorporated changes made to other board files. * Moved board files from board/nvidia to board/compal. * Switched to correct odmdata value. This required add the previous patch to fix U-Boot's interpretation of the odmdata RAM size field. * Removed nvmem= from default Linux kernel command-line; no drivers use the reserved memory yet, so there's no point reserving it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/compal/paz00')
-rw-r--r--board/compal/paz00/Makefile41
-rw-r--r--board/compal/paz00/paz00.c81
2 files changed, 122 insertions, 0 deletions
diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile
new file mode 100644
index 0000000..488e381
--- /dev/null
+++ b/board/compal/paz00/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../nvidia/common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+COBJS += ../../nvidia/common/board.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
new file mode 100644
index 0000000..3b48917
--- /dev/null
+++ b/board/compal/paz00/paz00.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/mmc.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Paz00 - no conflict w/SPI.
+ */
+void gpio_config_uart(void)
+{
+}
+
+#ifdef CONFIG_TEGRA2_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+ /* SDMMC4: config 3, x8 on 2nd set of pins */
+ pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+
+ pinmux_tristate_disable(PINGRP_ATB);
+ pinmux_tristate_disable(PINGRP_GMA);
+ pinmux_tristate_disable(PINGRP_GME);
+
+ /* SDMMC1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
+ pinmux_set_func(PINGRP_SDMMC1, PMUX_FUNC_SDIO1);
+
+ pinmux_tristate_disable(PINGRP_SDMMC1);
+
+ /* For power GPIO PV1 */
+ pinmux_tristate_disable(PINGRP_UAC);
+ /* For CD GPIO PI5 */
+ pinmux_tristate_disable(PINGRP_ATC);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ debug("board_mmc_init called\n");
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ debug("board_mmc_init: init eMMC\n");
+ /* init dev 0, eMMC chip, with 4-bit bus */
+ /* The board has an 8-bit bus, but 8-bit doesn't work yet */
+ tegra2_mmc_init(0, 4, -1, -1);
+
+ debug("board_mmc_init: init SD slot\n");
+ /* init dev 3, SD slot, with 4-bit bus */
+ tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PI5);
+
+ return 0;
+}
+#endif