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| author | wdenk <wdenk> | 2000-12-14 10:04:19 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2000-12-14 10:04:19 +0000 |
| commit | 2d39b71fb247a6462515be5ad7b167df740362d4 (patch) | |
| tree | 7d5df8b28e77680b66f2365e1240efe614e2286a /board/cogent/serial.h | |
| parent | 10af385938b938bb33ced12cc988c8277fe7e925 (diff) | |
| download | u-boot-imx-2d39b71fb247a6462515be5ad7b167df740362d4.zip u-boot-imx-2d39b71fb247a6462515be5ad7b167df740362d4.tar.gz u-boot-imx-2d39b71fb247a6462515be5ad7b167df740362d4.tar.bz2 | |
Initial revision
Diffstat (limited to 'board/cogent/serial.h')
| -rw-r--r-- | board/cogent/serial.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/board/cogent/serial.h b/board/cogent/serial.h new file mode 100644 index 0000000..89962d8 --- /dev/null +++ b/board/cogent/serial.h @@ -0,0 +1,15 @@ +/* Line Status Register bits */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#define CLKRATE 3686400 /* cogent motherboard serial clk = 3.6864MHz */ +#define DEFDIV 1 /* default to 230400 bps */ + +#define br_to_div(br) (CLKRATE / (16 * (br))) +#define div_to_br(div) (CLKRATE / (16 * (div))) |