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authorwdenk <wdenk>2004-11-21 00:06:33 +0000
committerwdenk <wdenk>2004-11-21 00:06:33 +0000
commit9d5028c2f7a65d3777867a6cfc966a01a5823132 (patch)
treec971cc2b0d41e422585c1911fffda7d2d6403ee4 /board/cmc_pu2/memsetup.S
parentcacfab588a897c369a4906818c5ed4bc40a450c5 (diff)
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* Update for AT91RM9200DK and CMC_PU2 boards:
- Enable booting directly from flash - fix CMC_PU2 flash driver * Fix mkimage usage message
Diffstat (limited to 'board/cmc_pu2/memsetup.S')
-rw-r--r--board/cmc_pu2/memsetup.S25
1 files changed, 15 insertions, 10 deletions
diff --git a/board/cmc_pu2/memsetup.S b/board/cmc_pu2/memsetup.S
index 2d0e1d7..b0c8d4c 100644
--- a/board/cmc_pu2/memsetup.S
+++ b/board/cmc_pu2/memsetup.S
@@ -6,7 +6,7 @@
*
* Modified for the at91rm9200dk board by
* (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -35,7 +35,7 @@
* some parameters for the board
*
* This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMMEL
+ * turn is based on the boot.bin code from ATMEL
*
*/
@@ -53,7 +53,7 @@
#define EBI_CFGR 0xFFFFFF64
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR 0xFFFFFF70
-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR 0xFFFFFC28
@@ -73,7 +73,7 @@
#define EBI_CSA 0xFFFFFF60
#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
#define SDRC_CR 0xFFFFFF98
-#define SDRC_CR_VAL 0x2188c155
+#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
#define SDRAM 0x20000000 /* address of the SDRAM */
#define SDRAM1 0x20000080 /* address of the SDRAM */
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
@@ -86,15 +86,20 @@
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-_TEXT_BASE:
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+ .word TEXT_BASE-PHYS_FLASH_1
+#else
.word TEXT_BASE
+#endif
-.globl memsetup
-memsetup:
+.globl lowlevelinit
+lowlevelinit:
/* memory control configuration */
/* this isn't very elegant, but what the heck */
ldr r0, =SMRDATA
- ldr r1, _TEXT_BASE
+ ldr r1, _MTEXT_BASE
sub r0, r0, r1
add r2, r0, #80
0:
@@ -106,12 +111,12 @@ memsetup:
cmp r2, r0
bne 0b
/* delay - this is all done by guess */
- ldr r0, =0x00001000
+ ldr r0, =0x00010000
1:
subs r0, r0, #1
bhi 1b
ldr r0, =SMRDATA1
- ldr r1, _TEXT_BASE
+ ldr r1, _MTEXT_BASE
sub r0, r0, r1
add r2, r0, #176
2: