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authorNishanth Menon <nm@ti.com>2013-03-26 05:20:49 +0000
committerTom Rini <trini@ti.com>2013-05-10 08:25:54 -0400
commit0208aaf6c2e0f346e8410c0e5adb0ea784f00829 (patch)
treef34a9e3197bf43352b92d2d673e3bc79bb75e138 /board/cm_t35
parentcd87464d0873d2db920e6b712ef34e9c83cfe5e6 (diff)
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twl4030: make twl4030_i2c_write_u8 prototype consistent
u-boot standard i2c register write prototype is i2c_reg_write(u8 addr, u8 reg, u8 val) twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val) Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'board/cm_t35')
-rw-r--r--board/cm_t35/cm_t35.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c
index 84c36ba..87d7354 100644
--- a/board/cm_t35/cm_t35.c
+++ b/board/cm_t35/cm_t35.c
@@ -493,17 +493,17 @@ static void setup_net_chip_gmpc(void)
static void reset_net_chip(void)
{
/* Set GPIO1 of TPS65930 as output */
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x03);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
+ 0x02);
/* Send a pulse on the GPIO pin */
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x0C);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+ 0x02);
udelay(1);
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x09);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
+ 0x02);
mdelay(40);
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x0C);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+ 0x02);
mdelay(1);
}
#else
@@ -600,10 +600,10 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
/* Set GPIO6 and GPIO7 of TPS65930 as output */
val |= 0xC0;
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
/* Take both PHYs out of reset */
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
udelay(1);
return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);