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author | Ira W. Snyder <iws@ovro.caltech.edu> | 2012-09-12 14:17:32 -0700 |
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committer | Kim Phillips <kim.phillips@freescale.com> | 2012-09-18 16:16:44 -0500 |
commit | ea1ea54e35e64386cc9eefbf0d96091430a7482a (patch) | |
tree | fdbede6b7a329162626a6822c53f9abc8657b92b /board/cm41xx | |
parent | f138ca1373d7ec9fca33ae21f1b5ff3898fd493f (diff) | |
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mpc8308rdb: add support for Spansion SPI flash on header J8
The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.
This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some of the TSEC pins.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'board/cm41xx')
0 files changed, 0 insertions, 0 deletions