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authorGabe Black <gabeblack@chromium.org>2012-10-10 13:12:57 +0000
committerSimon Glass <sjg@chromium.org>2012-11-28 11:40:04 -0800
commit452f50f7cff5d77db79ee3b11b4b3e19b166e6b0 (patch)
tree2e56873795ae70ca6d70aa7ad58c9babdb6b3281 /board/chromebook-x86
parentbadcb343d7844e81be92ba9a7a02f22159591650 (diff)
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x86: coreboot: Tell u-boot about PCI bus 0 when initializing
U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
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