* Added VIA configuration table

* Added support for PCI2 on CDS
  Patch by Andy Fleming 17-Mar-2006

Signed-off-by: Andy Fleming <afleming@freescale.com>

3 files changed, 29 insertions, 25 deletions

diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile
index aea6136..d202281 100644
--- a/board/cds/mpc8555cds/Makefile
+++ b/board/cds/mpc8555cds/Makefile
@@ -29,7 +29,8 @@ LIB	= lib$(BOARD).a
 OBJS	:= $(BOARD).o \
 	   ../common/cadmus.o \
 	   ../common/eeprom.o \
-	   ../common/ft_board.o
+	   ../common/ft_board.o \
+	   ../common/via.o
 
 SOBJS	:= init.o
 
diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S
index 53dcd0d..978bda5 100644
--- a/board/cds/mpc8555cds/init.S
+++ b/board/cds/mpc8555cds/init.S
@@ -210,8 +210,8 @@ tlb1_entry:
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
  * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
+ * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
  * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
@@ -234,11 +234,11 @@ tlb1_entry:
 #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
 #define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
 
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
-#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
 
 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c
index 18adf5b..e15bf8f 100644
--- a/board/cds/mpc8555cds/mpc8555cds.c
+++ b/board/cds/mpc8555cds/mpc8555cds.c
@@ -29,6 +29,7 @@
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
+#include "../common/via.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -464,38 +465,40 @@ testdram(void)
 }
 #endif
 
-#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device.  Work around that by refusing to configure it
  */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 
-#ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
-    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-      PCI_IDSEL_NUMBER, PCI_ANY_ID,
-      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				   PCI_ENET0_MEMADDR,
-				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
-      } },
-    { }
+	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
 };
-#endif
 
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
+
+static struct pci_controller hose[] = {
+	{
 	config_table: pci_mpc85xxcds_config_table,
+	},
+#ifdef CONFIG_MPC85XX_PCI2
+	{ }
 #endif
 };
 
-#endif	/* CONFIG_PCI */
+#endif
 
 void
 pci_init_board(void)
 {
 #ifdef CONFIG_PCI
-	extern void pci_mpc85xx_init(struct pci_controller *hose);
+	extern void pci_mpc85xx_init(struct pci_controller **hose);
 
-	pci_mpc85xx_init(&hose);
+	pci_mpc85xx_init(*pci_hose);
 #endif
 }