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authorAndy Fleming <afleming@freescale.com>2007-02-24 01:08:13 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-05-02 15:50:13 -0500
commitffa621a0d12a1ccd81c936c567f8917a213787a8 (patch)
tree3dcae45bdac750bb7a7cb377a975f0dbd5b70b3a /board/cds/mpc8548cds
parent6743105988fc44d5b0d30388c790607835aae7a6 (diff)
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Cleaned up some 85xx PCI bugs
* Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/cds/mpc8548cds')
-rw-r--r--board/cds/mpc8548cds/init.S2
-rw-r--r--board/cds/mpc8548cds/mpc8548cds.c9
2 files changed, 7 insertions, 4 deletions
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
index 34ca711..d468f5b 100644
--- a/board/cds/mpc8548cds/init.S
+++ b/board/cds/mpc8548cds/init.S
@@ -248,7 +248,7 @@ tlb1_entry:
#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR7 ((CFG_PEX_IO_BASE>>12) & 0xfffff)
+#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
index 0d3fceb..929ff2e 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -310,11 +310,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
+ {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+ {},
};
static struct pci_controller hose[] = {