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| author | Andy Fleming <afleming@freescale.com> | 2006-09-13 10:34:18 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2006-09-19 09:41:48 -0500 |
| commit | 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 (patch) | |
| tree | 64d49a225b13baa7ddae8792b1f9fb7c308e4990 /board/cds/mpc8548cds/mpc8548cds.c | |
| parent | 084d648b109c8984f83674043c1a7fa3885ef801 (diff) | |
| download | u-boot-imx-09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3.zip u-boot-imx-09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3.tar.gz u-boot-imx-09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3.tar.bz2 | |
Add support for eTSEC 3 & 4 on 8548 CDS
* Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS.
This will only work on rev 1.3 boards (but doesn't break older boards)
* Cleaned up some comments to reflect the expanded role of tsec
in other systems
Diffstat (limited to 'board/cds/mpc8548cds/mpc8548cds.c')
| -rw-r--r-- | board/cds/mpc8548cds/mpc8548cds.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 6eedb4a..66219e3 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -27,6 +27,7 @@ #include <asm/processor.h> #include <asm/immap_85xx.h> #include <spd.h> +#include <miiphy.h> #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -327,3 +328,34 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif } + +int last_stage_init(void) +{ + unsigned int temp; + + /* Change the resistors for the PHY */ + /* This is needed to get the RGMII working for the 1.3+ + * CDS cards */ + if (get_board_version() == 0x13) { + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 18); + + miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, &temp); + + temp = (temp & 0xf03f); + temp |= 2 << 9; /* 36 ohm */ + temp |= 2 << 6; /* 39 ohm */ + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, temp); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 3); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, 0x8000); + } + + return 0; +} |