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| author | Stefan Roese <sr@denx.de> | 2006-11-10 07:48:47 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2006-11-10 07:48:47 +0100 |
| commit | dfc8a9ee0040e53ada125a3c52f241e37f09cf28 (patch) | |
| tree | 60fd3973150a4e6b3d9d129d117ecab71b5edabe /board/cds/mpc8548cds/init.S | |
| parent | 5c912cb1c31266c66ca59b36f9b6f87296421d75 (diff) | |
| parent | 91650b3e4de688038d4f71279c44858e3e2c6870 (diff) | |
| download | u-boot-imx-dfc8a9ee0040e53ada125a3c52f241e37f09cf28.zip u-boot-imx-dfc8a9ee0040e53ada125a3c52f241e37f09cf28.tar.gz u-boot-imx-dfc8a9ee0040e53ada125a3c52f241e37f09cf28.tar.bz2 | |
Merge with /home/stefan/git/u-boot/denx
Diffstat (limited to 'board/cds/mpc8548cds/init.S')
| -rw-r--r-- | board/cds/mpc8548cds/init.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 53dcd0d..978bda5 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |