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| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /board/cds/mpc8541cds | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
| download | u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.zip u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.gz u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.bz2 | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'board/cds/mpc8541cds')
| -rw-r--r-- | board/cds/mpc8541cds/mpc8541cds.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index c75a4df..6b8aa68 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -32,7 +32,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -271,7 +271,7 @@ initdram(int board_type) #endif dram_size = spd_sdram(); -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ |