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author | Wolfgang Denk <wd@denx.de> | 2012-07-08 19:26:33 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2012-07-08 19:26:33 +0200 |
commit | 50cd93b25033764dcda9bb47aa68be778f94d36e (patch) | |
tree | b8606a377b805952d533300dfa1e98e42951678e /board/buffalo/lsxl/kwbimage-lschl.cfg | |
parent | 8246ff864de38935ff34108856a37a2caf6cbefc (diff) | |
parent | d702b0811df53a1fc2d8049e35431e4591d093c6 (diff) | |
download | u-boot-imx-50cd93b25033764dcda9bb47aa68be778f94d36e.zip u-boot-imx-50cd93b25033764dcda9bb47aa68be778f94d36e.tar.gz u-boot-imx-50cd93b25033764dcda9bb47aa68be778f94d36e.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
ARM: cache: Move the cp15 CR register read before flushing the cache.
ARM: introduce arch_early_init_r()
PXA: Enable CONFIG_PREBOOT on zipitz2
ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
No need to define CONFIG_ARCH_CPU_INIT.
add new board vl_ma2sc
MTD: SPEAr SMI: Add write support for length < 4 bytes
i2c: designware_i2c.c: Add support for the "i2c probe" command
rtc/m41t62: Add support for M41T82 with HT (Halt Update)
SPL: ARM: spear: Add SPL support for SPEAr600 platform
Makefile: Add u-boot.spr build target (SPEAr)
SPL: ARM: spear: Remove some objects from SPL build
SPL: lib/Makefile: Add crc32.c to SPL build
SPL: common/Makefile: Add image.c to SPL build
arm: Don't use printf() in SPL builds
GPIO: Add SPEAr GPIO driver
net: Multiple updates/enhancements to designware.c
cleanup/SPEAr: Define configuration flags more elegantly
cleanup/SPEAr: Remove unnecessary parenthesis
SPEAr: Correct SoC ID offset in misc configuration space
SPEAr: explicitly select clk src for UART
SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
SPEAr: Enable dcache for fast file transfer
SPEAr: Enable autoneg for ethernet
SPEAr: Enable udc and usb-console support only for usbtty configuration
SPEAr: Enable usb device high speed support
SPEAr: Initialize SNOR in early_board_init_f
SPEAr: Change the default environment variables
SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
SPEAr: Add configuration options for spear3xx and spear6xx boards
SPEAr: Add basic arch related support for SPEAr SoCs
SPEAr: Add interface information in initialization
SPEAr: Add macb driver support for spear310 and spear320
SPEAr: Configure network support for spear SoCs
SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
SPEAr: Eliminate dependency on Xloader table
SPEAr: Fix ARM relocation support
st_smi: Fixed page size for Winbond W25Q128FV flash
st_smi: Change timeout loop implementation
st_smi: Fix bug in flash_print_info()
st_smi: Change the flash probing method
st_smi: Removed no needed dependency on ST_M25Pxx_ID
st_smi: Fix smi read status
st_smi: Move status register read before modifying ctrl register
st_smi: Read status until timeout happens
st_smi: Enhance the error handling
st_smi: Change SMI timeout values
st_smi: Return error in case TFF is not set
st_smi: Add support for SPEAr SMI driver
mtd/NAND: Remove obsolete SPEAr specific NAND drivers
SPEAr: Configure FSMC driver for NAND interface
mtd/NAND: Add FSMC driver support
arm/km: remove calls to kw_gpio_* in board_early_init_f
arm/km: add implementation for read_dip_switch
arm/km: support the 2 PCIe fpga resets
arm/km: skip FPGA config when already configured
arm/km: redefine piggy 4 reg names to avoid conflicts
arm/km: cleanup km_kirkwood boards
arm/km: enable BOCO2 FPGA download support
arm/km: remove portl2.h and use km_kirkwood instead
arm/km: convert mgcoge3un target to km_kirkwood
arm/km: add kmcoge5un board support
arm/km: add kmnusa board support
arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
cm-t35: fix incorrect NAND_ECC layout selection
ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
ARM: OMAP4/5: Move USB pads to essential list.
ARM: OMAP4/5: Move USB clocks to essential group.
ARM: OMAP4/5: Move gpmc clocks to essential group.
ARM: OMAP4+: Move external phy initialisations to arch specific place.
omap4: Use a smaller M,N couple for IVA DPLL
da850/omap-l138: Enable auto negotiation in RMII mode
omap: am33xx: accomodate input clocks other than 24 Mhz
omap: emif: fix bug in manufacturer code test
omap: emif: deal with rams that return duplicate mr data on all byte lanes
OMAP4+: Force DDR in self-refresh after warm reset
OMAP4+: Handle sdram init after warm reset
ARM: OMAP3+: Detect reset type
arm: bugfix: Move vector table before jumping relocated code
Kirkwood: Add support for Ka-Ro TK71
arm/km: use spi claim bus to switch between SPI and NAND
arm/kirkwood: protect the ENV_SPI #defines
ARM: don't probe PHY address for LaCie boards
lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
lacie_kw: fix SDRAM banks number for net2big_v2
Kirkwood: add lschlv2 and lsxhl board support
net: add helper to generate random mac address
net: use common rand()/srand() functions
lib: add rand() function
kwboot: boot kirkwood SoCs over a serial link
kw_spi: add weak functions board_spi_claim/release_bus
kw_spi: support spi_claim/release_bus functions
kw_spi: backup and reset the MPP of the chosen CS pin
kirkwood: fix calls to kirkwood_mpp_conf
kirkwood: add save functionality kirkwood_mpp_conf function
km_arm: use filesize for erase in update command
arm/km: enable mii cmd
arm/km: remove CONFIG_RESET_PHY_R
arm/km: change maintainer for mgcoge3un
arm/km: fix wrong comment in SDRAM config for mgcoge3un
arm/km: use ARRAY_SIZE macro
arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
arm/km: add piggy mac adress offset for mgcoge3un
arm/km: add board type to boards.cfg
AT91SAM9*: Change kernel address in dataflash to match u-boot's size
ATMEL/PIO: Enable new feature of PIO on Atmel device
ehci-atmel: fix compiler warning
AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
Atmel : usb : add EHCI driver for Atmel SoC
Fix: AT91SAM9263 nor flash usage
Fix: broken boot message at serial line on AT91SAM9263-EK board
i.MX6 USDHC: Use the ESDHC clock
mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
i.MX28: Add function to adjust memory parameters
mx28evk: Fix PSWITCH key position
mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove unused CONFIG_MII_GASKET
mx6: Avoid writing to read-only bits in imximage.cfg
m28evk: use same notation to alloc the 128kB stack
...
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/buffalo/lsxl/kwbimage-lschl.cfg')
-rw-r--r-- | board/buffalo/lsxl/kwbimage-lschl.cfg | 229 |
1 files changed, 229 insertions, 0 deletions
diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg new file mode 100644 index 0000000..2b9b3cd --- /dev/null +++ b/board/buffalo/lsxl/kwbimage-lschl.cfg @@ -0,0 +1,229 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle <michael@walle.cc> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B1B9B + +# L2 RAM Timing 0 +DATA 0xFFD20134 0xBBBBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# L2 RAM Timing 1 +DATA 0xFFD20138 0x00BBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# DDR Configuration register +DATA 0xFFD01400 0x43000618 +# bit13-0: 0x618, 1560 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +# DDR Controller Control Low +DATA 0xFFD01404 0x39543000 +# bit3-0: 0 required +# bit4: 0, addr/cmd in same cycle +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +# DDR Timing (Low) +DATA 0xFFD01408 0x3302444F +# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0]) +# bit7-4: 4, 5 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 4, 5 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 0, 16 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 3, 4 cycle tRRD +# bit31-28: 3, 4 cyle tRTP + +# DDR Timing (High) +DATA 0xFFD0140C 0x00000823 +# bit6-0: 0x23, 35 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +# DDR Address Control +DATA 0xFFD01410 0x00000009 +# bit1-0: 1, Cs0width=x16 +# bit3-2: 2, Cs0size=512Mbit +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +# DDR Open Pages Control +DATA 0xFFD01414 0x00000000 +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +# DDR Operation +DATA 0xFFD01418 0x00000000 +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +# DDR Mode +DATA 0xFFD0141C 0x00000652 +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 3, Write recovery for auto-precharge (3 required) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +# DDR Extended Mode +DATA 0xFFD01420 0x00000042 +# bit0: 0, DRAM DLL enabled +# bit1: 1, DRAM drive strength reduced +# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) +# bit5-3: 0 required +# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +# DDR Controller Control High +DATA 0xFFD01424 0x0000F17F +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required (???) +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +# DDR2 ODT Read Timing (default values) +DATA 0xFFD01428 0x00085520 +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +# DDR2 ODT Write Timing (default values) +DATA 0xFFD0147C 0x00008552 +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +# CS[0]n Base address +DATA 0xFFD01500 0x00000000 +# at 0x0 + +# CS[0]n Size +DATA 0xFFD01504 0x03FFFFF1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x03, Size (i.e. 64MB) + +# CS[1]n Size +DATA 0xFFD0150C 0x00000000 +# window disabled + +# CS[2]n Size +DATA 0xFFD01514 0x00000000 +# window disabled + +# CS[3]n Size +DATA 0xFFD0151C 0x00000000 +# window disabled + +# DDR ODT Control (Low) +DATA 0xFFD01494 0x003C0000 +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3 +# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1 +# bit31-24: 0 required + +# DDR ODT Control (High) +DATA 0xFFD01498 0x00000000 +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +# CPU ODT Control +DATA 0xFFD0149C 0x0000E80F +# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +# DDR Initialization Control +DATA 0xFFD01480 0x00000001 +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 |