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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-15 15:18:31 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-15 15:18:31 +0100
commit6579d15c58e2b6b051f126ea8b77dd767252aa14 (patch)
treecac9f9205db8c28a764ad8282d3a909bf95e8db4 /board/boundary/nitrogen6x/clocks.cfg
parentc44bb3a30f5a1332176edce1a91c0e2cf666ee8f (diff)
parent19a0f7fa271de0345bb2df90d443c547c41e8037 (diff)
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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Diffstat (limited to 'board/boundary/nitrogen6x/clocks.cfg')
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1 files changed, 46 insertions, 0 deletions
diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg
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+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F