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authorGary Jennejohn <garyj@denx.de>2007-08-31 15:21:46 +0200
committerStefan Roese <sr@denx.de>2007-08-31 15:21:46 +0200
commit81b73dec16fd1227369a191e725e10044a9d56b8 (patch)
tree3d0fe0f95120227c7ced28cc3ff742e35d22dd71 /board/bf561-ezkit
parent9c02defc29b57945b600714cf61ddfd02b02fb14 (diff)
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ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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