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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/bf561-ezkit | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/bf561-ezkit')
| -rw-r--r-- | board/bf561-ezkit/bf561-ezkit.c | 10 | ||||
| -rw-r--r-- | board/bf561-ezkit/u-boot.lds.S | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 7345b42..a74ff0d 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -50,12 +50,12 @@ phys_size_t initdram(int board_type) printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); - printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); + printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); + printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); #endif - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; - return CFG_MAX_RAM_SIZE; + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return CONFIG_SYS_MAX_RAM_SIZE; } #if defined(CONFIG_MISC_INIT_R) diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S index ab5ef08..3defef4 100644 --- a/board/bf561-ezkit/u-boot.lds.S +++ b/board/bf561-ezkit/u-boot.lds.S @@ -36,7 +36,7 @@ * for different CPU's which may lack non-cache L1 data. */ #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CFG_MONITOR_BASE +# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE # define L1_DATA_B_SRAM_SIZE 0 #endif @@ -45,7 +45,7 @@ OUTPUT_ARCH(bfin) /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ MEMORY { - ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } |