diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2008-02-04 19:26:55 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2008-02-04 19:26:55 -0500 |
| commit | d4d7730853e5d675f76ec666807da3028c91d592 (patch) | |
| tree | db6cb9767a162b2b6a9d69a309956bbd75a0d6d8 /board/bf537-stamp/post-memory.c | |
| parent | 6cfcce67671a3425229d66203386fa3cbd0cc3bd (diff) | |
| download | u-boot-imx-d4d7730853e5d675f76ec666807da3028c91d592.zip u-boot-imx-d4d7730853e5d675f76ec666807da3028c91d592.tar.gz u-boot-imx-d4d7730853e5d675f76ec666807da3028c91d592.tar.bz2 | |
punt Blackfin VDSP headers and import sanitized/auto-generated ones
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'board/bf537-stamp/post-memory.c')
| -rw-r--r-- | board/bf537-stamp/post-memory.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 6039350..fa11991 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -104,15 +104,15 @@ void post_init_uart(int sclk) *pUART_GCTL = 0x00; *pUART_LCR = 0x83; - sync(); + SSYNC(); *pUART_DLL = (divisor & 0xFF); - sync(); + SSYNC(); *pUART_DLH = ((divisor >> 8) & 0xFF); - sync(); + SSYNC(); *pUART_LCR = 0x03; - sync(); + SSYNC(); *pUART_GCTL = 0x01; - sync(); + SSYNC(); } void post_out_buff(char *buff) @@ -124,7 +124,7 @@ void post_out_buff(char *buff) while ((buff[i] != '\0') && (i != 100)) { while (!(*pUART_LSR & 0x20)) ; *pUART_THR = buff[i]; - sync(); + SSYNC(); i++; } for (i = 0; i < 0x80000; i++) ; @@ -141,7 +141,7 @@ int post_key_pressed(void) *pPORTF_FER &= ~PF5; *pPORTFIO_DIR &= ~PF5; *pPORTFIO_INEN |= PF5; - sync(); + SSYNC(); post_out_buff("########Press SW10 to enter Memory POST########: 3\0"); for (i = 0; i < KEY_LOOP; i++) { @@ -303,7 +303,7 @@ int post_init_sdram(int sclk) (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS); - sync(); + SSYNC(); *pEBIU_SDGCTL |= 0x1000000; /* Set the SDRAM Refresh Rate control register based on SSCLK value */ @@ -314,7 +314,7 @@ int post_init_sdram(int sclk) /* SDRAM Memory Global Control Register */ *pEBIU_SDGCTL = mem_SDGCTL; - sync(); + SSYNC(); return mem_SDRRC; } |