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| author | Wolfgang Denk <wd@denx.de> | 2008-02-15 00:06:18 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-02-15 00:06:18 +0100 |
| commit | 6f99eec3dc2285abfb93631003f7e5cadf2eab0f (patch) | |
| tree | 1eaaa31eb768d8bfa68e9ff41eef53d37b64f21c /board/bf537-stamp/post-memory.c | |
| parent | f6921e3dc331293c873ec4d109fd5517a42a90b3 (diff) | |
| parent | 30942b18b66f35f2ceedab39af10e9eccaa943cc (diff) | |
| download | u-boot-imx-6f99eec3dc2285abfb93631003f7e5cadf2eab0f.zip u-boot-imx-6f99eec3dc2285abfb93631003f7e5cadf2eab0f.tar.gz u-boot-imx-6f99eec3dc2285abfb93631003f7e5cadf2eab0f.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-blackfin
Conflicts:
Makefile
doc/README.standalone
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/bf537-stamp/post-memory.c')
| -rw-r--r-- | board/bf537-stamp/post-memory.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 6039350..fa11991 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -104,15 +104,15 @@ void post_init_uart(int sclk) *pUART_GCTL = 0x00; *pUART_LCR = 0x83; - sync(); + SSYNC(); *pUART_DLL = (divisor & 0xFF); - sync(); + SSYNC(); *pUART_DLH = ((divisor >> 8) & 0xFF); - sync(); + SSYNC(); *pUART_LCR = 0x03; - sync(); + SSYNC(); *pUART_GCTL = 0x01; - sync(); + SSYNC(); } void post_out_buff(char *buff) @@ -124,7 +124,7 @@ void post_out_buff(char *buff) while ((buff[i] != '\0') && (i != 100)) { while (!(*pUART_LSR & 0x20)) ; *pUART_THR = buff[i]; - sync(); + SSYNC(); i++; } for (i = 0; i < 0x80000; i++) ; @@ -141,7 +141,7 @@ int post_key_pressed(void) *pPORTF_FER &= ~PF5; *pPORTFIO_DIR &= ~PF5; *pPORTFIO_INEN |= PF5; - sync(); + SSYNC(); post_out_buff("########Press SW10 to enter Memory POST########: 3\0"); for (i = 0; i < KEY_LOOP; i++) { @@ -303,7 +303,7 @@ int post_init_sdram(int sclk) (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS); - sync(); + SSYNC(); *pEBIU_SDGCTL |= 0x1000000; /* Set the SDRAM Refresh Rate control register based on SSCLK value */ @@ -314,7 +314,7 @@ int post_init_sdram(int sclk) /* SDRAM Memory Global Control Register */ *pEBIU_SDGCTL = mem_SDGCTL; - sync(); + SSYNC(); return mem_SDRRC; } |