punt Blackfin VDSP headers and import sanitized/auto-generated ones

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2 files changed, 36 insertions, 35 deletions

diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 69e425b..af03597 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -76,9 +76,9 @@ void swap_to(int device_id)
 
 	if (device_id == ETHERNET) {
 		*pFIO_DIR = PF0;
-		sync();
+		SSYNC();
 		*pFIO_FLAG_S = PF0;
-		sync();
+		SSYNC();
 	} else if (device_id == FLASH) {
 		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
 		*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@@ -88,7 +88,7 @@ void swap_to(int device_id)
 		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_FLAG_D = (PF4 | PF3 | PF2);
-		sync();
+		SSYNC();
 	} else {
 		printf("Unknown bank to switch\n");
 	}
@@ -155,15 +155,15 @@ void cf_outb(unsigned char val, volatile unsigned char *addr)
 	 */
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	*(addr) = val;
-	sync();
+	SSYNC();
 
 	/* Setback PF1 PF0 to 0 0 to address external
 	 * memory banks  */
 	*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 
 unsigned char cf_inb(volatile unsigned char *addr)
@@ -172,13 +172,13 @@ unsigned char cf_inb(volatile unsigned char *addr)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	c = *(addr);
-	sync();
+	SSYNC();
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 
 	return c;
 }
@@ -189,15 +189,15 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	for (i = 0; i < words; i++) {
 		*(sect_buf + i) = *(addr);
-		sync();
+		SSYNC();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 
 void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@@ -206,15 +206,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	for (i = 0; i < words; i++) {
 		*(addr) = *(sect_buf + i);
-		sync();
+		SSYNC();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 #endif
 
@@ -235,7 +235,7 @@ void stamp_led_set(int LED1, int LED2, int LED3)
 		*pFIO_FLAG_S = PF4;
 	else
 		*pFIO_FLAG_C = PF4;
-	sync();
+	SSYNC();
 }
 
 void show_boot_progress(int status)
diff --git a/board/bf533-stamp/spi.c b/board/bf533-stamp/spi.c
index d30750f..15141cf 100644
--- a/board/bf533-stamp/spi.c
+++ b/board/bf533-stamp/spi.c
@@ -4,6 +4,7 @@
 #include <common.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/spi.h>
 
 #if defined(CONFIG_SPI)
 
@@ -153,7 +154,7 @@ void SendSingleCommand(const int iCommand)
 
 	/*sends the actual command to the SPI TX register */
 	*pSPI_TDBR = iCommand;
-	sync();
+	SSYNC();
 
 	/*The SPI status register will be polled to check the SPIF bit */
 	Wait_For_SPIF();
@@ -174,7 +175,7 @@ void SetupSPI(const int spi_setting)
 	*pSPI_FLG = 0xFB04;
 	*pSPI_BAUD = CONFIG_SPI_BAUD;
 	*pSPI_CTL = spi_setting;
-	sync();
+	SSYNC();
 }
 
 void SPI_OFF(void)
@@ -183,7 +184,7 @@ void SPI_OFF(void)
 	*pSPI_CTL = 0x0400;	/* disable SPI */
 	*pSPI_FLG = 0;
 	*pSPI_BAUD = 0;
-	sync();
+	SSYNC();
 	udelay(CONFIG_CCLK_HZ / 50000000);
 
 }
@@ -241,10 +242,10 @@ char ReadStatusRegister(void)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
 
 	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the data has been sent */
 	status_register = *pSPI_RDBR;	/*read the status register */
 
@@ -305,18 +306,18 @@ ERROR_CODE EraseBlock(int nBlock)
 	/* Send the erase block command to the flash followed by the 24 address  */
 	/* to point to the start of a sector. */
 	*pSPI_TDBR = SPI_SE;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();
 	ShiftValue = (ulSectorOff >> 16);	/* Send the highest byte of the 24 bit address at first */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulSectorOff >> 8);	/* Send the middle byte of the 24 bit address  at second */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	*pSPI_TDBR = ulSectorOff;	/* Send the lowest byte of the 24 bit address finally */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 
 	/*Turns off the SPI */
@@ -351,25 +352,25 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
 
 	*pSPI_TDBR = SPI_READ;	/* Send the read command to SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulStart >> 16);	/* Send the highest byte of the 24 bit address at first */
 	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulStart >> 8);	/* Send the middle byte of the 24 bit address  at second */
 	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	*pSPI_TDBR = ulStart;	/* Send the lowest byte of the 24 bit address finally */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 
 	/* After the SPI device address has been placed on the MOSI pin the data can be */
 	/* received on the MISO pin. */
 	for (i = 0; i < lCount; i++) {
 		*pSPI_TDBR = 0;	/*send dummy */
-		sync();
+		SSYNC();
 		while (!(*pSPI_STAT & RXS)) ;
 		*cnData++ = *pSPI_RDBR;	/*read  */
 
@@ -406,26 +407,26 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
 		/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
 		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turns the SPI on */
 	*pSPI_TDBR = SPI_PP;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = (ulStartAddr >> 16);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = (ulStartAddr >> 8);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = ulStartAddr;
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
 	/* and sent to the SPI device. */
 	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
 		iData = *temp;
 		*pSPI_TDBR = iData;
-		sync();
+		SSYNC();
 		Wait_For_SPIF();	/*wait until the instruction has been sent */
 		temp++;
 	}