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authorDirk Behme <dirk.behme@de.bosch.com>2012-04-12 20:46:14 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-04-17 15:41:22 +0200
commit03f3587822839d90b1b118d3cd51c59d8b4d5b32 (patch)
treeb97f9f4b0fd8160339a223544285a72479b7af71 /board/bf525-ucr2
parentf5cdc11775c4b7fdbf52a6dd2f463d329804ab11 (diff)
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i.MX6: arm2: Add AXI cache and Qos setting
Do the same AXI cache and Qos settings done already in the SabreLite imximage.cfg for the ARM2 board, too. It fixes a display flash issue caused by low priority of the display IDMA channel. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com> Acked-by: Jason Liu <r64343@freescale.com>
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