summaryrefslogtreecommitdiff
path: root/board/barco
diff options
context:
space:
mode:
authorPeng Fan <Peng.Fan@freescale.com>2015-08-17 16:11:03 +0800
committerStefano Babic <sbabic@denx.de>2015-09-02 15:34:12 +0200
commitf2ff834365296151b24bf8617f1f6dd070bdce9e (patch)
treebfe6c4b1a6a55061a28e64df5e4933124eb5673e /board/barco
parent003fa83c437f62f7558a7f7408b7cd7c31c01276 (diff)
downloadu-boot-imx-f2ff834365296151b24bf8617f1f6dd070bdce9e.zip
u-boot-imx-f2ff834365296151b24bf8617f1f6dd070bdce9e.tar.gz
u-boot-imx-f2ff834365296151b24bf8617f1f6dd070bdce9e.tar.bz2
imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper. The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg when ddr_type is for DDR3. Later we can use ddr_type to initialize MMDC for LPDDR2. Initialize ddr_type for different boards which enable SPL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/barco')
-rw-r--r--board/barco/platinum/spl_picon.c1
-rw-r--r--board/barco/platinum/spl_titanium.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c
index f421c21..098542f 100644
--- a/board/barco/platinum/spl_picon.c
+++ b/board/barco/platinum/spl_picon.c
@@ -137,6 +137,7 @@ static void spl_dram_init(int width)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c
index 26fe26b..a3a4255 100644
--- a/board/barco/platinum/spl_titanium.c
+++ b/board/barco/platinum/spl_titanium.c
@@ -140,6 +140,7 @@ static void spl_dram_init(int width)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);