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| author | Andy Fleming <afleming@freescale.com> | 2008-09-09 16:16:20 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-09-09 16:16:20 -0500 |
| commit | 650a9e7abc44ce1ce73d6668eaf0ba2d6b8025e9 (patch) | |
| tree | 30732e12d39390eda22338e98db7b8ab9025bf22 /board/avnet/v5fx30teval/xparameters.h | |
| parent | 6cc64f9b5f69239c8b1969572b5a3a4aab7de5b9 (diff) | |
| parent | 3b20fd83c73c22acfcb0c6663be747bd5c8b7011 (diff) | |
| download | u-boot-imx-650a9e7abc44ce1ce73d6668eaf0ba2d6b8025e9.zip u-boot-imx-650a9e7abc44ce1ce73d6668eaf0ba2d6b8025e9.tar.gz u-boot-imx-650a9e7abc44ce1ce73d6668eaf0ba2d6b8025e9.tar.bz2 | |
Merge branch 'denx'
Diffstat (limited to 'board/avnet/v5fx30teval/xparameters.h')
| -rw-r--r-- | board/avnet/v5fx30teval/xparameters.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h new file mode 100644 index 0000000..bb657fc --- /dev/null +++ b/board/avnet/v5fx30teval/xparameters.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters.h by Xilinx + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif |