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| author | Lucas Stach <dev@lynxeye.de> | 2012-09-25 20:21:13 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:07 -0700 |
| commit | 65530a842eeaf7ad07e0613ac6f883f2f1f1e33f (patch) | |
| tree | 01e704c3bbf59d1c5f7be1ba55ae8dcf656a5128 /board/avionic-design | |
| parent | 3f44e44f33899821c4703c3bd5f9c117bb328e8b (diff) | |
| download | u-boot-imx-65530a842eeaf7ad07e0613ac6f883f2f1f1e33f.zip u-boot-imx-65530a842eeaf7ad07e0613ac6f883f2f1f1e33f.tar.gz u-boot-imx-65530a842eeaf7ad07e0613ac6f883f2f1f1e33f.tar.bz2 | |
tegra20: add clock_set_pllout function
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.
This function adds a clean way to do so.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/avionic-design')
0 files changed, 0 insertions, 0 deletions