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authorAllen Martin <amartin@nvidia.com>2013-01-16 13:12:24 +0000
committerTom Warren <twarren@nvidia.com>2013-01-17 09:07:34 -0700
commitb7723f3f303d3b847e1adcb226328f432fe4b233 (patch)
tree46ca76644a6566bb844fcf310ae1864ca1fb50bf /board/avionic-design/dts
parentd3f8752ed60cbd18022aee0afb7784754c125170 (diff)
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tegra: fdt: sort dts files
Sort nodes in dts files according the the following rules: 1) Any nodes that already exist in any /include/d file, in the order they appear in the /include/d file. 2) Any nodes with a reg property, in order of their address. 3) Any nodes without a reg property, alphabetically by node name. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/avionic-design/dts')
-rw-r--r--board/avionic-design/dts/tegra20-tec.dts22
1 files changed, 11 insertions, 11 deletions
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index 8135eeb..bf3ff1d 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -31,6 +31,17 @@
clock-frequency = <216000000>;
};
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+ };
+
i2c@7000c000 {
status = "disabled";
};
@@ -55,17 +66,6 @@
status = "disabled";
};
- nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
- nvidia,width = <8>;
- nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-
- nand@0 {
- reg = <0>;
- compatible = "hynix,hy27uf4g2b", "nand-flash";
- };
- };
-
lcd_panel: panel {
clock = <33260000>;
xres = <800>;