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authorTom Rini <trini@ti.com>2013-02-12 10:18:31 -0500
committerTom Rini <trini@ti.com>2013-02-12 10:18:31 -0500
commit951c6baaf44c7fd4335b75fb92840d4e42c94927 (patch)
tree6a09cce20c4f3affb7b500d018eb84f848e42c20 /board/avionic-design/dts/tegra20-tec.dts
parent58864ddc7276ca7403ddbb716da5853638f37519 (diff)
parentfd8e1c3866578d87ed14a04a59faae341fd415df (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'board/avionic-design/dts/tegra20-tec.dts')
-rw-r--r--board/avionic-design/dts/tegra20-tec.dts56
1 files changed, 37 insertions, 19 deletions
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index 50ea3b5..bf3ff1d 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -14,24 +14,34 @@
reg = <0x00000000 0x20000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
- };
+ host1x {
+ status = "okay";
- osc {
- clock-frequency = <12000000>;
- };
- };
+ dc@54200000 {
+ status = "okay";
- clock@60006000 {
- clocks = <&clk_32k &osc>;
+ rgb {
+ nvidia,panel = <&lcd_panel>;
+ status = "okay";
+ };
+ };
};
serial@70006300 {
clock-frequency = <216000000>;
};
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+ };
+
i2c@7000c000 {
status = "disabled";
};
@@ -56,14 +66,22 @@
status = "disabled";
};
- nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
- nvidia,width = <8>;
- nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-
- nand@0 {
- reg = <0>;
- compatible = "hynix,hy27uf4g2b", "nand-flash";
- };
+ lcd_panel: panel {
+ clock = <33260000>;
+ xres = <800>;
+ yres = <480>;
+ left-margin = <120>;
+ right-margin = <120>;
+ hsync-len = <16>;
+ lower-margin = <15>;
+ upper-margin = <15>;
+ vsync-len = <15>;
+
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 0 500000>;
+ nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,panel-timings = <0 0 0 0>;
};
};