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author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-02 09:03:08 -0500 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-08 09:10:07 -0500 |
commit | 3e7b6c1f2db5ec31f9e7dbc3e0cbca602167a46a (patch) | |
tree | a10000c36ecf3385327c86e27955a74718e67680 /board/atum8548 | |
parent | 5052a771cf1722c37c732f3c340775b55fbe3a22 (diff) | |
download | u-boot-imx-3e7b6c1f2db5ec31f9e7dbc3e0cbca602167a46a.zip u-boot-imx-3e7b6c1f2db5ec31f9e7dbc3e0cbca602167a46a.tar.gz u-boot-imx-3e7b6c1f2db5ec31f9e7dbc3e0cbca602167a46a.tar.bz2 |
ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host
Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.
Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/atum8548')
-rw-r--r-- | board/atum8548/atum8548.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 85c0adc..a220ad4 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -202,8 +202,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -262,7 +262,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; - uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ |