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authorWolfgang Denk <wd@denx.de>2008-01-10 00:55:14 +0100
committerWolfgang Denk <wd@denx.de>2008-01-10 00:55:14 +0100
commitd3a6532cbe263d992f49e86ac95bede28e96f9c8 (patch)
tree687561d091203e912658d34422fb969eb7ab3744 /board/atum8548
parent694976afa5dcc5c4e7eaeaa0612eac35cd5bd8ec (diff)
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Coding Style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/atum8548')
-rw-r--r--board/atum8548/atum8548.c6
-rw-r--r--board/atum8548/init.S22
2 files changed, 14 insertions, 14 deletions
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index 4d7dc77..f11abd8 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -140,7 +140,7 @@ testdram(void)
for (p = pstart; p < pend; p++) {
printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
*p = 0xaaaaaaaa;
- }
+ }
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
@@ -191,7 +191,7 @@ pci_init_board(void)
debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
- /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
+ /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
gur->clkocr |= MPC85xx_ATUM_CLKOCR;
if (io_sel & 1) {
@@ -376,7 +376,7 @@ pci_init_board(void)
int last_stage_init(void)
{
- int ic = icache_status ();
+ int ic = icache_status ();
printf ("icache_status: %d\n", ic);
return 0;
}
diff --git a/board/atum8548/init.S b/board/atum8548/init.S
index a410e2e..654a569 100644
--- a/board/atum8548/init.S
+++ b/board/atum8548/init.S
@@ -70,7 +70,7 @@ tlb1_entry:
/*
* Number of TLB0 and TLB1 entries in the following table
*/
- .long (2f-1f)/16
+ .long (2f-1f)/16
1:
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
@@ -182,15 +182,15 @@ tlb1_entry:
/*
* LAW(Local Access Window) configuration:
*
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
- * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
- * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M
- * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
+ * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
+ * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
@@ -227,7 +227,7 @@ law_entry:
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)