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authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:26 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:29 -0500
commita1d558a20f1eaeae9927abc4e0978725d33bae53 (patch)
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powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the transmit data vs DQS paths. During this calibration, the DDR controller may make an inaccurate calculation, resulting in a non-optimal tap point. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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