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| author | Heiko Schocher <hs@denx.de> | 2014-07-18 06:07:22 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-07-23 12:31:34 +0200 |
| commit | e379c03902e55aed2533f569727e006d3ec4b9c3 (patch) | |
| tree | f99744819670b05ca2e32183f18eb4f08284a7ac /board/aristainetos/ddr-setup.cfg | |
| parent | 562f8df18da62ae02c4ace1e530451fe82c3312d (diff) | |
| download | u-boot-imx-e379c03902e55aed2533f569727e006d3ec4b9c3.zip u-boot-imx-e379c03902e55aed2533f569727e006d3ec4b9c3.tar.gz u-boot-imx-e379c03902e55aed2533f569727e006d3ec4b9c3.tar.bz2 | |
arm, imx6: add aristainetos board
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
Board: aristaitenos
I2C: ready
DRAM: 1 GiB
NAND: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Display: lb07wv8 (800x480)
- UART5 is console
- MMC 0 and 1
- USB 0 and 1
- boot from mmc0 and spi nor flash
- Splash screen support
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/aristainetos/ddr-setup.cfg')
| -rw-r--r-- | board/aristainetos/ddr-setup.cfg | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg new file mode 100644 index 0000000..c72a3ef --- /dev/null +++ b/board/aristainetos/ddr-setup.cfg @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* Clock */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +/* Address */ +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* Control */ +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* Data Strobe */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 |