Merge git://www.denx.de/git/u-boot

12 files changed, 652 insertions, 90 deletions

diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
new file mode 100644
index 0000000..abcbf3e
--- /dev/null
+++ b/board/amcc/acadia/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o cpr.o memory.o
+SOBJS	=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
new file mode 100644
index 0000000..baf598c
--- /dev/null
+++ b/board/amcc/acadia/acadia.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+extern void board_pll_init_f(void);
+
+static void acadia_gpio_init(void)
+{
+	/*
+	 * GPIO0 setup (select GPIO or alternate function)
+	 */
+       	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+       	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
+       	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+       	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
+       	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+       	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
+       	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
+
+	/*
+	 * Ultra (405EZ) was nice enough to add another GPIO controller
+	 */
+	out32(GPIO1_OSRH, CFG_GPIO1_OSRH);	/* output select */
+	out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
+	out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H);	/* input select */
+	out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
+	out32(GPIO1_TSRH, CFG_GPIO1_TSRH);	/* three-state select */
+	out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
+	out32(GPIO1_TCR, CFG_GPIO1_TCR);  /* enable output driver for outputs */
+}
+
+int board_early_init_f(void)
+{
+	unsigned int reg;
+
+	/* don't reinit PLL when booting via I2C bootstrap option */
+	mfsdr(SDR_PINSTP, reg);
+	if (reg != 0xf0000000)
+		board_pll_init_f();
+
+	acadia_gpio_init();
+
+	/* USB Host core needs this bit set */
+	mfsdr(sdrultra1, reg);
+	mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000010);
+	mtdcr(uicpr, 0xFE7FFFF0);	/* set int polarities */
+	mtdcr(uictr, 0x00000010);	/* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+int misc_init_f(void)
+{
+	/* Set EPLD to take PHY out of reset */
+	out8(CFG_CPLD_BASE + 0x05, 0x00);
+	udelay(100000);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk
new file mode 100644
index 0000000..c8566ec
--- /dev/null
+++ b/board/amcc/acadia/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFC0000
+endif
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c
new file mode 100644
index 0000000..9dcce35
--- /dev/null
+++ b/board/amcc/acadia/cpr.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc405.h>
+
+/* test-only: move into cpu directory!!! */
+
+#if defined(PLLMR0_200_133_66)
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  200.0     |   4 (0x02)|
+	 * | PLB   |  133.3     |   6 (0x06)|
+	 * | OPB   |   66.6     |  12 (0x0C)|
+	 * | EBC   |   66.6     |  12 (0x0C)|
+	 * | SPI   |   66.6     |  12 (0x0C)|
+	 * | UART0 |   10.0     |  40 (0x28)|
+	 * | UART1 |   10.0     |  40 (0x28)|
+	 * | DAC   |    2.0     | 200 (0xC8)|
+	 * | ADC   |    2.0     | 200 (0xC8)|
+	 * | PWM   |  100.0     |   4 (0x04)|
+	 * | EMAC  |   25.0     |  16 (0x10)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc, 0x0000033c);
+	mtcpr(cprplld, 0x0c010200);
+	mtcpr(cprprimad, 0x04060c0c);
+	mtcpr(cprperd0, 0x000c0000);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_266_160_80)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  266.64    |   3       |
+	 * | PLB   |  159.98    |   5 (0x05)|
+	 * | OPB   |   79.99    |  10 (0x0A)|
+	 * | EBC   |   79.99    |  10 (0x0A)|
+	 * | SPI   |   79.99    |  10 (0x0A)|
+	 * | UART0 |   28.57    |   7 (0x07)|
+	 * | UART1 |   28.57    |   7 (0x07)|
+	 * | DAC   |   28.57    |   7 (0xA7)|
+	 * | ADC   |    4       |  50 (0x32)|
+	 * | PWM   |   28.57    |   7 (0x07)|
+	 * | EMAC  |    4       |  50 (0x32)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc, 0x20000238);
+	mtcpr(cprplld, 0x03010400);
+	mtcpr(cprprimad, 0x03050a0a);
+	mtcpr(cprperc0, 0x00000000);
+	mtcpr(cprperd0, 0x070a0707);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1, 0x07323200);
+	mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_333_166_83)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  333.33    |   2       |
+	 * | PLB   |  166.66    |   4 (0x04)|
+	 * | OPB   |   83.33    |   8 (0x08)|
+	 * | EBC   |   83.33    |   8 (0x08)|
+	 * | SPI   |   83.33    |   8 (0x08)|
+	 * | UART0 |   16.66    |   5 (0x05)|
+	 * | UART1 |   16.66    |   5 (0x05)|
+	 * | DAC   |   ????     | 166 (0xA6)|
+	 * | ADC   |   ????     | 166 (0xA6)|
+	 * | PWM   |   41.66    |   3 (0x03)|
+	 * | EMAC  |   ????     |   3 (0x03)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc, 0x0000033C);
+	mtcpr(cprplld, 0x0a010000);
+	mtcpr(cprprimad, 0x02040808);
+	mtcpr(cprperd0, 0x02080505);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1, 0xA6A60300);
+	mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_100_100_12)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------
+	 * | CLK   | FREQ (MHz) |
+	 * ----------------------
+	 * | CPU   |  100.00    |
+	 * | PLB   |  100.00    |
+	 * | OPB   |   12.00    |
+	 * | EBC   |   49.00    |
+	 * ----------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc, 0x000003BC);
+	mtcpr(cprplld, 0x06060600);
+	mtcpr(cprprimad, 0x02020004);
+	mtcpr(cprperd0, 0x04002828);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1, 0xC8C81600);
+	mtcpr(cprclkupd, 0x40000000);
+}
+#endif				/* CPU_<speed>_405EZ */
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk(void)
+{
+	unsigned long cpr_plld;
+	unsigned long cpr_primad;
+	unsigned long primad_cpudv;
+	unsigned long pllFbkDiv;
+	unsigned long freqProcessor;
+
+	/*
+	 * Read PLL Mode registers
+	 */
+	mfcpr(cprplld, cpr_plld);
+
+	/*
+	 * Read CPR_PRIMAD register
+	 */
+	mfcpr(cprprimad, cpr_primad);
+
+	/*
+	 * Determine CPU clock frequency
+	 */
+	primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+	if (primad_cpudv == 0)
+		primad_cpudv = 16;
+
+	/*
+	 * Determine FBK_DIV.
+	 */
+	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+	if (pllFbkDiv == 0)
+		pllFbkDiv = 256;
+
+	freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
+
+	return (freqProcessor);
+}
+#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
new file mode 100644
index 0000000..5375d36
--- /dev/null
+++ b/board/amcc/acadia/memory.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+	return;
+}
+
+static void cram_bcr_write(u32 wr_val)
+{
+	wr_val <<= 2;
+
+	/* set CRAM_CRE to 1 */
+	gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
+
+	/* Write BCR to CRAM on CS1 */
+	out32(wr_val + 0x00200000, 0);
+	debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
+
+	/* Write BCR to CRAM on CS2 */
+	out32(wr_val + 0x02200000, 0);
+	debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
+
+	sync();
+	eieio();
+
+	/* set CRAM_CRE back to 0 (normal operation) */
+	gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
+
+	return;
+}
+
+long int initdram(int board_type)
+{
+	u32 val;
+
+	/* 1. EBC need to program READY, CLK, ADV for ASync mode */
+	gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
+
+	/* 2. EBC in Async mode */
+	mtebc(pb1ap, 0x078F1EC0);
+	mtebc(pb2ap, 0x078F1EC0);
+	mtebc(pb1cr, 0x000BC000);
+	mtebc(pb2cr, 0x020BC000);
+
+	/* 3. Set CRAM in Sync mode */
+	cram_bcr_write(0x7012);		/* CRAM burst setting */
+
+	/* 4. EBC in Sync mode */
+	mtebc(pb1ap, 0x9C0201C0);
+	mtebc(pb2ap, 0x9C0201C0);
+
+	/* Set GPIO pins back to alternate function */
+	gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+	gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+
+	/* Config EBC to use RDY */
+	mfsdr(sdrultra0, val);
+	mtsdr(sdrultra0, val | 0x04000000);
+
+	return (CFG_MBYTES_RAM << 20);
+}
+
+int testdram(void)
+{
+	return (0);
+}
diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds
new file mode 100644
index 0000000..b08c999
--- /dev/null
+++ b/board/amcc/acadia/u-boot.lds
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index c93ba6e..b5bb145 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/gpio.h>
 #include <spd_sdram.h>
 #include <ppc440.h>
 #include "bamboo.h"
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
index 1ce6366..4474862 100644
--- a/board/amcc/bamboo/bamboo.h
+++ b/board/amcc/bamboo/bamboo.h
@@ -264,19 +264,9 @@
 #define TRUE 1
 #define FALSE 0
 
-#define GPIO_GROUP_MAX	    2
-#define GPIO_MAX	    32
-#define GPIO_ALT1_SEL	    0x40000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
-#define GPIO_ALT2_SEL	    0x80000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
-#define GPIO_ALT3_SEL	    0xC0000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
-#define GPIO_MASK	    0xC0000000	    /* GPIO_MASK */
-#define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
-					    /* For the other GPIO number, you must shift */
-
 #define GPIO0		0
 #define GPIO1		1
 
-
 /*#define MAX_SELECTION_NB	CORE_NB */
 #define MAX_CORE_SELECT_NB	22
 
diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c
index 684f6a5..439be4f 100644
--- a/board/amcc/katmai/cmd_katmai.c
+++ b/board/amcc/katmai/cmd_katmai.c
@@ -27,6 +27,9 @@
 #include <i2c.h>
 #include <asm/byteorder.h>
 
+#define	CONFIG_STRESS		/* enable 667 MHz CPU freq selection */
+#define DEBUG
+
 static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	uchar	chip;
@@ -49,55 +52,28 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	else
 		chip = IIC0_ALT_BOOTPROM_ADDR;
 
-	do {
-		printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
-		nbytes = readline (" ? ");
-
-		if (strcmp(console_buffer, "quit") == 0)
-			return 0;
-
-		if ((strcmp(console_buffer, "33") != 0) &
-		    (strcmp(console_buffer, "66") != 0))
-			nbytes=0;
-
-		strcpy(sysClock, console_buffer);
-
-	} while (nbytes == 0);
+	/* on Katmai SysClk is always 33MHz */
+	strcpy(sysClock, "33");
 
 	do {
-		if (strcmp(sysClock, "66") == 0) {
-			printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
-		} else {
 #ifdef	CONFIG_STRESS
-			printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
+		printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
 #else
-			printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
+		printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
 #endif
-		}
 		nbytes = readline (" ? ");
 
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
 
-		if (strcmp(sysClock, "66") == 0) {
-			if ((strcmp(console_buffer, "400") != 0) &
-			    (strcmp(console_buffer, "533") != 0)
-#ifdef	CONFIG_STRESS
-			    & (strcmp(console_buffer, "667") != 0)
-#endif
-				) {
-				nbytes = 0;
-			}
-		} else {
-			if ((strcmp(console_buffer, "400") != 0) &
-			    (strcmp(console_buffer, "500") != 0) &
-			    (strcmp(console_buffer, "533") != 0)
+		if ((strcmp(console_buffer, "400") != 0) &&
+		    (strcmp(console_buffer, "500") != 0) &&
+		    (strcmp(console_buffer, "533") != 0)
 #ifdef	CONFIG_STRESS
-			    & (strcmp(console_buffer, "667") != 0)
+		    && (strcmp(console_buffer, "667") != 0)
 #endif
-				) {
-				nbytes = 0;
-			}
+			) {
+			nbytes = 0;
 		}
 
 		strcpy(cpuClock, console_buffer);
@@ -124,13 +100,13 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 				return 0;
 
 			if (strcmp(cpuClock, "400") == 0) {
-				if ((strcmp(console_buffer, "100") != 0) &
+				if ((strcmp(console_buffer, "100") != 0) &&
 				    (strcmp(console_buffer, "133") != 0))
 					nbytes = 0;
 			}
 #ifdef	CONFIG_STRESS
 			if (strcmp(cpuClock, "667") == 0) {
-				if ((strcmp(console_buffer, "133") != 0) &
+				if ((strcmp(console_buffer, "133") != 0) &&
 				    (strcmp(console_buffer, "166") != 0))
 					nbytes = 0;
 			}
@@ -147,9 +123,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
 
-		if ((strcmp(console_buffer, "33") != 0) &
-		    (strcmp(console_buffer, "66") != 0) &
-		    (strcmp(console_buffer, "100") != 0) &
+		if ((strcmp(console_buffer, "33") != 0) &&
+		    (strcmp(console_buffer, "66") != 0) &&
+		    (strcmp(console_buffer, "100") != 0) &&
 		    (strcmp(console_buffer, "133") != 0)) {
 			nbytes = 0;
 		}
@@ -176,11 +152,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	} while (nbytes == 0);
 
 	if (strcmp(sysClock, "33") == 0) {
-		if ((strcmp(cpuClock, "400") == 0) &
+		if ((strcmp(cpuClock, "400") == 0) &&
 		    (strcmp(plbClock, "100") == 0))
 			data = 0x8678c206;
 
-		if ((strcmp(cpuClock, "400") == 0) &
+		if ((strcmp(cpuClock, "400") == 0) &&
 		    (strcmp(plbClock, "133") == 0))
 			data = 0x8678c2c6;
 
@@ -189,42 +165,16 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 		if ((strcmp(cpuClock, "533") == 0))
 			data = 0x87790252;
-
 #ifdef	CONFIG_STRESS
-		if ((strcmp(cpuClock, "667") == 0) &
+		if ((strcmp(cpuClock, "667") == 0) &&
 		    (strcmp(plbClock, "133") == 0))
 			data = 0x87794256;
 
-		if ((strcmp(cpuClock, "667") == 0) &
+		if ((strcmp(cpuClock, "667") == 0) &&
 		    (strcmp(plbClock, "166") == 0))
 			data = 0x87794206;
-
-#endif
-	}
-	if (strcmp(sysClock, "66") == 0) {
-		if ((strcmp(cpuClock, "400") == 0) &
-		    (strcmp(plbClock, "100") == 0))
-			data = 0x84706206;
-
-		if ((strcmp(cpuClock, "400") == 0) &
-		    (strcmp(plbClock, "133") == 0))
-			data = 0x847062c6;
-
-		if ((strcmp(cpuClock, "533") == 0))
-			data = 0x85708206;
-
-#ifdef	CONFIG_STRESS
-		if ((strcmp(cpuClock, "667") == 0) &
-		    (strcmp(plbClock, "133") == 0))
-			data = 0x8570a256;
-
-		if ((strcmp(cpuClock, "667") == 0) &
-		    (strcmp(plbClock, "166") == 0))
-			data = 0x8570a206;
-
 #endif
 	}
-
 #ifdef	DEBUG
 	printf(" pin strap0 to write in i2c  = %x\n", data);
 #endif	/* DEBUG */
@@ -233,19 +183,20 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		printf("Error writing strap0 in %s\n", argv[2]);
 
 	if (strcmp(pcixClock, "33") == 0)
-		data = 0x00000701;
+		data = 0x000007E1;
 
 	if (strcmp(pcixClock, "66") == 0)
-		data = 0x00000601;
+		data = 0x000006E1;
 
 	if (strcmp(pcixClock, "100") == 0)
-		data = 0x00000501;
+		data = 0x000005E1;
 
 	if (strcmp(pcixClock, "133") == 0)
-		data = 0x00000401;
+		data = 0x000004E1;
 
 	if (strcmp(plbClock, "166") == 0)
-		data |= 0x05950000;
+/*		data |= 0x05950000; */	/* this set's DDR2 clock == PLB clock */
+		data |= 0x05A50000;	/* this set's DDR2 clock == 2 * PLB clock */
 	else
 		data |= 0x05A50000;
 
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index 6b024ee..5202ae6 100644
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -103,7 +103,7 @@ tlbtabB:
 
 	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
 
 	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index fbf1a98..286bdc1 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <i2c.h>
 #include <asm-ppc/io.h>
+#include <asm-ppc/gpio.h>
 
 #include "../cpu/ppc4xx/440spe_pcie.h"
 
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index daaffe0..930fa71 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -363,8 +363,8 @@ int checkboard(void)
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = *(u8 *)(CFG_CPLD + 0);
-	val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+	rev = *(u8 *)(CFG_BCSR_BASE + 0);
+	val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {