Merge git://www.denx.de/git/u-boot

Conflicts:

	CREDITS

38 files changed, 3085 insertions, 354 deletions

diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
index abcbf3e..c56b273 100644
--- a/board/amcc/acadia/Makefile
+++ b/board/amcc/acadia/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cpr.o memory.o
+COBJS	= $(BOARD).o cmd_acadia.o memory.o pll.o
 SOBJS	=
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index baf598c..8b82ea4 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -31,13 +31,13 @@ static void acadia_gpio_init(void)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-       	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-       	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
-       	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-       	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
-       	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-       	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
-       	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
+	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
+	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
+	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
+	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
 
 	/*
 	 * Ultra (405EZ) was nice enough to add another GPIO controller
@@ -55,13 +55,25 @@ int board_early_init_f(void)
 {
 	unsigned int reg;
 
+#if !defined(CONFIG_NAND_U_BOOT)
 	/* don't reinit PLL when booting via I2C bootstrap option */
 	mfsdr(SDR_PINSTP, reg);
 	if (reg != 0xf0000000)
 		board_pll_init_f();
+#endif
 
 	acadia_gpio_init();
 
+	/* Configure 405EZ for NAND usage */
+	mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
+	mfsdr(sdrultra0, reg);
+	reg &= ~SDR_ULTRA0_CSN_MASK;
+	reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) |
+		SDR_ULTRA0_NDGPIOBP |
+		SDR_ULTRA0_EBCRDYEN |
+		SDR_ULTRA0_NFSRSTEN;
+	mtsdr(sdrultra0, reg);
+
 	/* USB Host core needs this bit set */
 	mfsdr(sdrultra1, reg);
 	mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
@@ -91,8 +103,11 @@ int misc_init_f(void)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
+	u8 rev;
+
+	rev = in8(CFG_CPLD_BASE + 0);
+	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
 
-	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);
diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c
new file mode 100644
index 0000000..fb7ea35
--- /dev/null
+++ b/board/amcc/acadia/cmd_acadia.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+static u8 boot_267_nor[] = {
+	0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00,
+	0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00
+};
+
+static u8 boot_267_nand[] = {
+	0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00,
+	0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00
+};
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u8 chip;
+	u8 *buf;
+	int cpu_freq;
+
+	if (argc < 3) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	cpu_freq = simple_strtol(argv[1], NULL, 10);
+	if (cpu_freq != 267) {
+		printf("Unsupported cpu-frequency - only 267 supported\n");
+		return 1;
+	}
+
+	/* use 0x50 as I2C EEPROM address for now */
+	chip = 0x50;
+
+	if ((strcmp(argv[2], "nor") != 0) &&
+	    (strcmp(argv[2], "nand") != 0)) {
+		printf("Unsupported boot-device - only nor|nand support\n");
+		return 1;
+	}
+
+	if (strcmp(argv[2], "nand") == 0) {
+		switch (cpu_freq) {
+		case 267:
+			buf = boot_267_nand;
+			break;
+		default:
+			break;
+		}
+	} else {
+		switch (cpu_freq) {
+		case 267:
+			buf = boot_267_nor;
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (i2c_write(chip, 0, 1, buf, 16) != 0)
+		printf("Error writing to EEPROM at address 0x%x\n", chip);
+	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+	if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
+		printf("Error2 writing to EEPROM at address 0x%x\n", chip);
+
+	printf("Done\n");
+	printf("Please power-cycle the board for the changes to take effect\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bootstrap,	3,	0,	do_bootstrap,
+	"bootstrap - program the I2C bootstrap EEPROM\n",
+	"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
+	);
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk
index c8566ec..af5a46c 100644
--- a/board/amcc/acadia/config.mk
+++ b/board/amcc/acadia/config.mk
@@ -21,6 +21,12 @@
 # MA 02111-1307 USA
 #
 
+#
+# AMCC 405EZ Reference Platform (Acadia) board
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xFFFC0000
 endif
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 5375d36..9346d2c 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -31,6 +31,8 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
+extern void board_pll_init_f(void);
+
 /*
  * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
  */
@@ -39,6 +41,7 @@ void sdram_init(void)
 	return;
 }
 
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 static void cram_bcr_write(u32 wr_val)
 {
 	wr_val <<= 2;
@@ -62,9 +65,21 @@ static void cram_bcr_write(u32 wr_val)
 
 	return;
 }
+#endif
 
 long int initdram(int board_type)
 {
+#if defined(CONFIG_NAND_SPL)
+	u32 reg;
+
+	/* don't reinit PLL when booting via I2C bootstrap option */
+	mfsdr(SDR_PINSTP, reg);
+	if (reg != 0xf0000000)
+		board_pll_init_f();
+#endif
+
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	int i;
 	u32 val;
 
 	/* 1. EBC need to program READY, CLK, ADV for ASync mode */
@@ -92,7 +107,12 @@ long int initdram(int board_type)
 
 	/* Config EBC to use RDY */
 	mfsdr(sdrultra0, val);
-	mtsdr(sdrultra0, val | 0x04000000);
+	mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
+
+	/* Wait a short while, since for NAND booting this is too fast */
+	for (i=0; i<200000; i++)
+		;
+#endif
 
 	return (CFG_MBYTES_RAM << 20);
 }
diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/pll.c
index 9dcce35..9dcce35 100644
--- a/board/amcc/acadia/cpr.c
+++ b/board/amcc/acadia/pll.c
diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds
new file mode 100644
index 0000000..a5dae0e
--- /dev/null
+++ b/board/amcc/acadia/u-boot-nand.lds
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/environment.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
index 5da96e9..d01cc49 100644
--- a/board/amcc/bamboo/Makefile
+++ b/board/amcc/bamboo/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002-2006
+# (C) Copyright 2002-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -33,7 +33,7 @@ OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 6260b01..00c793a 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -32,9 +32,170 @@ void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 int is_nand_selected(void);
 
-unsigned char cfg_simulate_spd_eeprom[128];
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+/*************************************************************************
+ *
+ * Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ *	13 row add bits, 10 column add bits (but 12 row used only).
+ *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ *	12 row add bits, 10 column add bits.
+ *	Prepare a subset (only the used ones) of SPD data
+ *
+ *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ *	the corresponding bank is divided by 2 due to number of Row addresses
+ *	12 in the ECC module
+ *
+ *  Assumes:	64 MB, ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+const unsigned char cfg_simulate_spd_eeprom[128] = {
+	0x80,    /* number of SPD bytes used: 128 */
+	0x08,    /*  total number bytes in SPD device = 256 */
+	0x07,    /* DDR ram */
+#ifdef CONFIG_DDR_ECC
+	0x0C,    /* num Row Addr: 12 */
+#else
+	0x0D,    /* num Row Addr: 13 */
+#endif
+	0x09,    /* numColAddr: 9  */
+	0x01,    /* numBanks: 1 */
+	0x20,    /* Module data width: 32 bits */
+	0x00,    /* Module data width continued: +0 */
+	0x04,    /* 2.5 Volt */
+	0x75,    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+#ifdef CONFIG_DDR_ECC
+	0x02,    /* ECC ON : 02 OFF : 00 */
+#else
+	0x00,    /* ECC ON : 02 OFF : 00 */
+#endif
+	0x82,    /* refresh Rate Type: Normal (15.625us) + Self refresh */
+	0,
+	0,
+	0,
+	0x01,    /* wcsbc = 1 */
+	0,
+	0,
+	0x0C,    /* casBit (2,2.5) */
+	0,
+	0,
+	0x00,    /* not registered: 0  registered : 0x02*/
+	0,
+	0xA0,    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+	0,
+	0x00,    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+	0,
+	0x50,    /* tRpNs = 20 ns  */
+	0,
+	0x50,    /* tRcdNs = 20 ns */
+	45,      /* tRasNs */
+#ifdef CONFIG_DDR_ECC
+	0x08,    /* bankSizeID: 32MB */
+#else
+	0x10,    /* bankSizeID: 64MB */
+#endif
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0
+};
+#endif
 
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
 #if 0
 {	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
     {
@@ -291,73 +452,18 @@ int checkboard(void)
 	return (0);
 }
 
-/*************************************************************************
- *
- * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
- *
- * Fixed memory is composed of :
- *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- *	13 row add bits, 10 column add bits (but 12 row used only).
- *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- *	12 row add bits, 10 column add bits.
- *	Prepare a subset (only the used ones) of SPD data
- *
- *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- *	the corresponding bank is divided by 2 due to number of Row addresses
- *	12 in the ECC module
- *
- *  Assumes:	64 MB, ECC, non-registered
- *		PLB @ 133 MHz
- *
- ************************************************************************/
-static void init_spd_array(void)
-{
-	cfg_simulate_spd_eeprom[8]     = 0x04;    /* 2.5 Volt */
-	cfg_simulate_spd_eeprom[2]     = 0x07;    /* DDR ram */
-
-#ifdef CONFIG_DDR_ECC
-	cfg_simulate_spd_eeprom[11]    = 0x02;    /* ECC ON : 02 OFF : 00 */
-	cfg_simulate_spd_eeprom[31]    = 0x08;    /* bankSizeID: 32MB */
-	cfg_simulate_spd_eeprom[3]     = 0x0C;    /* num Row Addr: 12 */
-#else
-	cfg_simulate_spd_eeprom[11]    = 0x00;    /* ECC ON : 02 OFF : 00 */
-	cfg_simulate_spd_eeprom[31]    = 0x10;    /* bankSizeID: 64MB */
-	cfg_simulate_spd_eeprom[3]     = 0x0D;    /* num Row Addr: 13 */
-#endif
-
-	cfg_simulate_spd_eeprom[4]     = 0x09;    /* numColAddr: 9  */
-	cfg_simulate_spd_eeprom[5]     = 0x01;    /* numBanks: 1 */
-	cfg_simulate_spd_eeprom[0]     = 0x80;    /* number of SPD bytes used: 128 */
-	cfg_simulate_spd_eeprom[1]     = 0x08;    /*  total number bytes in SPD device = 256 */
-	cfg_simulate_spd_eeprom[21]    = 0x00;    /* not registered: 0  registered : 0x02*/
-	cfg_simulate_spd_eeprom[6]     = 0x20;    /* Module data width: 32 bits */
-	cfg_simulate_spd_eeprom[7]     = 0x00;    /* Module data width continued: +0 */
-	cfg_simulate_spd_eeprom[15]    = 0x01;    /* wcsbc = 1 */
-	cfg_simulate_spd_eeprom[27]    = 0x50;    /* tRpNs = 20 ns  */
-	cfg_simulate_spd_eeprom[29]    = 0x50;    /* tRcdNs = 20 ns */
-
-	cfg_simulate_spd_eeprom[30]    = 45;      /* tRasNs */
-
-	cfg_simulate_spd_eeprom[18]    = 0x0C;    /* casBit (2,2.5) */
-
-	cfg_simulate_spd_eeprom[9]     = 0x75;    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
-	cfg_simulate_spd_eeprom[23]    = 0xA0;    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
-	cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
-	cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */
-}
 
 long int initdram (int board_type)
 {
-	long dram_size = 0;
-
-	/*
-	 * First write simulated values in eeprom array for onboard bank 0
-	 */
-	init_spd_array();
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+	long dram_size;
 
 	dram_size = spd_sdram();
 
 	return dram_size;
+#else
+	return CFG_MBYTES_SDRAM << 20;
+#endif
 }
 
 #if defined(CFG_DRAM_TEST)
@@ -365,11 +471,12 @@ int testdram(void)
 {
 	unsigned long *mem = (unsigned long *)0;
 	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
+	unsigned long k, n, *p32, ctr;
+	const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
 
 	mtmsr(0);
 
-	for (k = 0; k < CFG_KBYTES_SDRAM;
+	for (k = 0; k <	CFG_MBYTES_SDRAM*1024;
 	     ++k, mem += (1024 / sizeof(unsigned long))) {
 		if ((k & 1023) == 0) {
 			printf("%3d MB\r", k / 1024);
@@ -393,6 +500,34 @@ int testdram(void)
 			}
 		}
 	}
+
+	/*
+	 * Perform a sequence test to ensure that all
+	 * memory locations are uniquely addressable
+	 */
+	ctr = 0;
+	p32 = 0;
+	while ((unsigned long)p32 != bend) {
+		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+			printf("Writing	%3d MB\r", (unsigned long)p32 >> 20);
+		*p32++ = ctr++;
+	}
+
+	ctr = 0;
+	p32 = 0;
+	while ((unsigned long)p32 != bend) {
+		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+			printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
+
+		if (*p32 != ctr) {
+			printf("SDRAM test fails at: %08x\n", p32);
+			return 1;
+		}
+
+		ctr++;
+		p32++;
+	}
+
 	printf("SDRAM test passes\n");
 	return 0;
 }
@@ -410,7 +545,7 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
@@ -451,7 +586,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
@@ -881,11 +1016,11 @@ void ext_bus_cntlr_init(void)
 		/*------------------------------------------------------------------------- */
 	case BOOT_FROM_NAND_FLASH0:
 		/*------------------------------------------------------------------------- */
-		ebc0_cs0_bnap_value = 0;
-		ebc0_cs0_bncr_value = 0;
+		ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
+		ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 
-		ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
-		ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+		ebc0_cs1_bnap_value = 0;
+		ebc0_cs1_bncr_value = 0;
 		ebc0_cs2_bnap_value = 0;
 		ebc0_cs2_bncr_value = 0;
 		ebc0_cs3_bnap_value = 0;
@@ -1205,7 +1340,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config)
 /*----------------------------------------------------------------------------+
   | init_default_gpio
   +----------------------------------------------------------------------------*/
-void init_default_gpio(void)
+void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	int i;
 
@@ -1275,7 +1410,7 @@ void init_default_gpio(void)
   |
   +----------------------------------------------------------------------------*/
 
-void update_uart_ios(uart_config_nb_t uart_config)
+void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	switch (uart_config)
 	{
@@ -1403,16 +1538,16 @@ void update_uart_ios(uart_config_nb_t uart_config)
 /*----------------------------------------------------------------------------+
   | update_ndfc_ios(void).
   +----------------------------------------------------------------------------*/
-void update_ndfc_ios(void)
+void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	/* Update GPIO Configuration Table */
 	gpio_tab[GPIO0][6].in_out = GPIO_OUT;	    /* EBC_CS_N(1) */
 	gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
 
-#if 0
 	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(2) */
 	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
 
+#if 0
 	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(3) */
 	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
 #endif
@@ -1421,7 +1556,7 @@ void update_ndfc_ios(void)
 /*----------------------------------------------------------------------------+
   | update_zii_ios(void).
   +----------------------------------------------------------------------------*/
-void update_zii_ios(void)
+void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	/* Update GPIO Configuration Table */
 	gpio_tab[GPIO0][12].in_out = GPIO_IN;	    /* ZII_p0Rxd(0) */
@@ -1471,7 +1606,7 @@ void update_zii_ios(void)
 /*----------------------------------------------------------------------------+
   | update_uic_0_3_irq_ios().
   +----------------------------------------------------------------------------*/
-void update_uic_0_3_irq_ios(void)
+void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO1][8].in_out = GPIO_IN;	    /* UIC_IRQ(0) */
 	gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
@@ -1489,7 +1624,7 @@ void update_uic_0_3_irq_ios(void)
 /*----------------------------------------------------------------------------+
   | update_uic_4_9_irq_ios().
   +----------------------------------------------------------------------------*/
-void update_uic_4_9_irq_ios(void)
+void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO1][12].in_out = GPIO_IN;	    /* UIC_IRQ(4) */
 	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
@@ -1510,7 +1645,7 @@ void update_uic_4_9_irq_ios(void)
 /*----------------------------------------------------------------------------+
   | update_dma_a_b_ios().
   +----------------------------------------------------------------------------*/
-void update_dma_a_b_ios(void)
+void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO1][12].in_out = GPIO_OUT;	    /* DMA_ACK(1) */
 	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
@@ -1531,7 +1666,7 @@ void update_dma_a_b_ios(void)
 /*----------------------------------------------------------------------------+
   | update_dma_c_d_ios().
   +----------------------------------------------------------------------------*/
-void update_dma_c_d_ios(void)
+void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][0].in_out = GPIO_IN;	    /* DMA_REQ(2) */
 	gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
@@ -1556,7 +1691,7 @@ void update_dma_c_d_ios(void)
 /*----------------------------------------------------------------------------+
   | update_ebc_master_ios().
   +----------------------------------------------------------------------------*/
-void update_ebc_master_ios(void)
+void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* EXT_EBC_REQ */
 	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
@@ -1574,7 +1709,7 @@ void update_ebc_master_ios(void)
 /*----------------------------------------------------------------------------+
   | update_usb2_device_ios().
   +----------------------------------------------------------------------------*/
-void update_usb2_device_ios(void)
+void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][26].in_out = GPIO_IN;	    /* USB2D_RXVALID */
 	gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
@@ -1605,20 +1740,21 @@ void update_usb2_device_ios(void)
 /*----------------------------------------------------------------------------+
   | update_pci_patch_ios().
   +----------------------------------------------------------------------------*/
-void update_pci_patch_ios(void)
+void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
 	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
 }
 
 /*----------------------------------------------------------------------------+
-  |   set_chip_gpio_configuration(unsigned char gpio_core)
+  |   set_chip_gpio_configuration(unsigned char gpio_core,
+  |                               gpio_param_s (*gpio_tab)[GPIO_MAX])
   |   Put the core impacted by clock modification and sharing in reset.
   |   Config the select registers to resolve the sharing depending of the config.
   |   Configure the GPIO registers.
   |
   +----------------------------------------------------------------------------*/
-void set_chip_gpio_configuration(unsigned char gpio_core)
+void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	unsigned char i=0, j=0, reg_offset = 0;
 	unsigned long gpio_reg, gpio_core_add;
@@ -1772,11 +1908,12 @@ void configure_ppc440ep_pins(void)
 			CORE_NOT_SELECTED	/* PCI_PATCH */
 		};
 
+	gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
 
 	/* Table Default Initialisation + FPGA Access */
-	init_default_gpio();
-	set_chip_gpio_configuration(GPIO0);
-	set_chip_gpio_configuration(GPIO1);
+	init_default_gpio(gpio_tab);
+	set_chip_gpio_configuration(GPIO0, gpio_tab);
+	set_chip_gpio_configuration(GPIO1, gpio_tab);
 
 	/* Update Table */
 	force_bup_core_selection(ppc440ep_core_selection, &config_val);
@@ -1811,7 +1948,7 @@ void configure_ppc440ep_pins(void)
 	/* UIC 0:3 Selection */
 	if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
 	{
-		update_uic_0_3_irq_ios();
+		update_uic_0_3_irq_ios(gpio_tab);
 		dma_a_b_unselect_in_fpga();
 	}
 
@@ -1819,21 +1956,21 @@ void configure_ppc440ep_pins(void)
 	if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
-		update_uic_4_9_irq_ios();
+		update_uic_4_9_irq_ios(gpio_tab);
 	}
 
 	/* DMA AB Selection */
 	if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
-		update_dma_a_b_ios();
+		update_dma_a_b_ios(gpio_tab);
 		dma_a_b_selection_in_fpga();
 	}
 
 	/* DMA CD Selection */
 	if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
 	{
-		update_dma_c_d_ios();
+		update_dma_c_d_ios(gpio_tab);
 		dma_c_d_selection_in_fpga();
 	}
 
@@ -1842,14 +1979,14 @@ void configure_ppc440ep_pins(void)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
-		update_ebc_master_ios();
+		update_ebc_master_ios(gpio_tab);
 	}
 
 	/* PCI Patch Enable */
 	if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
-		update_pci_patch_ios();
+		update_pci_patch_ios(gpio_tab);
 	}
 
 	/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
@@ -1865,7 +2002,7 @@ void configure_ppc440ep_pins(void)
 	/* USB2.0 Device Selection */
 	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
 	{
-		update_usb2_device_ios();
+		update_usb2_device_ios(gpio_tab);
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
 
@@ -1898,14 +2035,23 @@ void configure_ppc440ep_pins(void)
 	/* NAND Flash Selection */
 	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
 	{
-		update_ndfc_ios();
+		update_ndfc_ios(gpio_tab);
 
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 		mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
 		      SDR0_CUST0_NDFC_ENABLE	|
 		      SDR0_CUST0_NDFC_BW_8_BIT	|
 		      SDR0_CUST0_NDFC_ARE_MASK	|
 		      SDR0_CUST0_CHIPSELGAT_EN1 |
 		      SDR0_CUST0_CHIPSELGAT_EN2);
+#else
+		mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
+		      SDR0_CUST0_NDFC_ENABLE	|
+		      SDR0_CUST0_NDFC_BW_8_BIT	|
+		      SDR0_CUST0_NDFC_ARE_MASK	|
+		      SDR0_CUST0_CHIPSELGAT_EN0 |
+		      SDR0_CUST0_CHIPSELGAT_EN2);
+#endif
 
 		ndfc_selection_in_fpga();
 	}
@@ -1918,7 +2064,7 @@ void configure_ppc440ep_pins(void)
 	/* MII Selection */
 	if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
 	{
-		update_zii_ios();
+		update_zii_ios(gpio_tab);
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
 		mtsdr(sdr_mfr, sdr0_mfr);
@@ -1929,7 +2075,7 @@ void configure_ppc440ep_pins(void)
 	/* RMII Selection */
 	if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
 	{
-		update_zii_ios();
+		update_zii_ios(gpio_tab);
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
 		mtsdr(sdr_mfr, sdr0_mfr);
@@ -1940,7 +2086,7 @@ void configure_ppc440ep_pins(void)
 	/* SMII Selection */
 	if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
 	{
-		update_zii_ios();
+		update_zii_ios(gpio_tab);
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
 		mtsdr(sdr_mfr, sdr0_mfr);
@@ -1977,7 +2123,7 @@ void configure_ppc440ep_pins(void)
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
 		break;
 	}
-	update_uart_ios(uart_configuration);
+	update_uart_ios(uart_configuration, gpio_tab);
 
 	/* UART Selection in all cases */
 	uart_selection_in_fpga(uart_configuration);
@@ -1999,8 +2145,8 @@ void configure_ppc440ep_pins(void)
 
 	/* Perform effective access to hardware */
 	mtsdr(sdr_pfc1, sdr0_pfc1);
-	set_chip_gpio_configuration(GPIO0);
-	set_chip_gpio_configuration(GPIO1);
+	set_chip_gpio_configuration(GPIO0, gpio_tab);
+	set_chip_gpio_configuration(GPIO1, gpio_tab);
 
 	/* USB2.0 Device Reset must be done after GPIO setting */
 	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
index 9d7f4c3..b46527d 100644
--- a/board/amcc/bamboo/config.mk
+++ b/board/amcc/bamboo/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002-2006
+# (C) Copyright 2002-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,7 +21,11 @@
 # MA 02111-1307 USA
 #
 
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
 TEXT_BASE = 0xFFFA0000
+endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
index a30ab7a..8a2e832 100644
--- a/board/amcc/bamboo/flash.c
+++ b/board/amcc/bamboo/flash.c
@@ -53,7 +53,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
 	{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
 	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
-	{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
+	{0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash  */
 	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
 	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
 	{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
@@ -134,10 +134,10 @@ unsigned long flash_init(void)
 		flash_info[i].size = 0;
 
 		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0) {
+		if (flash_addr_table[index][i] == 0)
 			continue;
-		}
 
+		DEBUGF("Detection bank %d...\n", i);
 		/* call flash_get_size() to initialize sector address */
 		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
 				   &flash_info[i]);
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 7820107..f4d2ae3 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -1,74 +1,31 @@
 /*
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 
 #include <ppc_asm.tmpl>
 #include <config.h>
-
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K	    0x00000000
-#define SZ_4K	    0x00000010
-#define SZ_16K	    0x00000020
-#define SZ_64K	    0x00000030
-#define SZ_256K	    0x00000040
-#define SZ_1M	    0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M	    0x00000070
-#define SZ_256M	    0x00000090
-
-/* Storage attributes */
-#define SA_W	    0x00000800	    /* Write-through */
-#define SA_I	    0x00000400	    /* Caching inhibited */
-#define SA_M	    0x00000200	    /* Memory coherence */
-#define SA_G	    0x00000100	    /* Guarded */
-#define SA_E	    0x00000080	    /* Endian */
-
-/* Access control */
-#define AC_X	    0x00000024	    /* Execute */
-#define AC_W	    0x00000012	    /* Write */
-#define AC_R	    0x00000009	    /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)		( (a)&0x00000fbf )
-
-#define tlbtab_start\
-	mflr    r1  ;\
-	bl 0f	    ;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;   \
-0:	mflr    r0	;   \
-	mtlr    r1	;   \
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -80,34 +37,67 @@
  *  Pointer to the table is returned in r1
  *
  *************************************************************************/
-
-    .section .bootpg,"ax"
-    .globl tlbtab
+	.section .bootpg,"ax"
+	.globl tlbtab
 
 tlbtab:
-    tlbtab_start
-
-    /*
-     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-     * speed up boot process. It is patched after relocation to enable SA_I
-     */
-    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
-
-    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
-
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
-    tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
-
-    /* PCI */
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
-
-    /* USB 2.0 Device */
-    tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
-
-    tlbtab_end
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+#ifndef CONFIG_NAND_SPL
+	tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+#else
+	tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+#endif
+
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+
+	/* PCI base & peripherals */
+	tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+	tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+
+	/* PCI */
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
+
+	/* USB 2.0 Device */
+	tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
+
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 0)
+#define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,0x0000		/* TLB entry #0 */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif
diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds
new file mode 100644
index 0000000..a5dae0e
--- /dev/null
+++ b/board/amcc/bamboo/u-boot-nand.lds
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/environment.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
index f6d7183..0375618 100644
--- a/board/amcc/bamboo/u-boot.lds
+++ b/board/amcc/bamboo/u-boot.lds
@@ -141,8 +141,6 @@ SECTIONS
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
   _end = . ;
   PROVIDE (end = .);
 }
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index fe6ce8a..66e7509 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -20,10 +20,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-long int spd_sdram(void);
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
+
+long int spd_sdram(void);
 
 int board_early_init_f(void)
 {
@@ -34,6 +36,15 @@ int board_early_init_f(void)
 	mtdcr(uictr, 0x00000010);	/* set int trigger levels */
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 
+	/*
+	 * Configure CPC0_PCI to enable PerWE as output
+	 * and enable the internal PCI arbiter if selected
+	 */
+	if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
+		mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+	else
+		mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
+
 	return 0;
 }
 
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index e6429ec..eba0511 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -745,19 +745,27 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
 		if (info->flash_id & FLASH_BTYPE) {
 			/* set sector offsets for bottom boot block type */
 			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000a000;
+			info->start[6] = base + 0x0000c000;
+			info->start[7] = base + 0x0000e000;
+			for (i = 8; i < info->sector_count; i++) {
 				info->start[i] =
-				    base + (i * 0x00010000) - 0x00030000;
+				    base + ((i-7) * 0x00010000);
 			}
 		} else {
 			/* set sector offsets for top boot block type */
 			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00002000;
 			info->start[i--] = base + info->size - 0x00004000;
 			info->start[i--] = base + info->size - 0x00006000;
 			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000a000;
+			info->start[i--] = base + info->size - 0x0000c000;
+			info->start[i--] = base + info->size - 0x0000e000;
 			for (; i >= 0; i--) {
 				info->start[i] = base + i * 0x00010000;
 			}
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index dcafac9..ededb3e 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -207,14 +207,14 @@ long int fixed_sdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long strap;
 
 	/*--------------------------------------------------------------------------+
-     *	The ebony board is always configured as the host & requires the
-     *	PCI arbiter to be enabled.
+	 * The ebony board is always configured as the host & requires the
+	 * PCI arbiter to be enabled.
 	 *--------------------------------------------------------------------------*/
 	strap = mfdcr(cpc0_strp1);
 	if ((strap & 0x00100000) == 0) {
@@ -224,7 +224,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index 5202ae6..e3f3da6 100644
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -67,9 +67,9 @@ tlbtabA:
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -109,9 +109,9 @@ tlbtabB:
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 286bdc1..a49066f 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -34,6 +34,8 @@
 #undef PCIE_ENDPOINT
 /* #define PCIE_ENDPOINT 1 */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int ppc440spe_init_pcie_rootport(int port);
 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
 
@@ -292,7 +294,7 @@ int testdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -309,7 +311,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
@@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
@@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
 	struct pci_controller *hose;
 	int i, bus;
+	char *env;
+	unsigned int delay;
 
 	/*
 	 * assume we're called after the PCIX hose is initialized, which takes
 	 * bus ID 0 and therefore start numbering PCIe's from 1.
 	 */
-	bus = 1;
+	bus = busno;
 	for (i = 0; i <= 2; i++) {
 		/* Check for katmai card presence */
 		if (!katmai_pcie_card_present(i))
@@ -418,8 +420,8 @@ void pcie_setup_hoses(void)
 
 		hose = &pcie_hose[i];
 		hose->first_busno = bus;
-		hose->last_busno  = bus;
-		bus++;
+		hose->last_busno = bus;
+		hose->current_busno = bus;
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
@@ -439,10 +441,21 @@ void pcie_setup_hoses(void)
 		 */
 #else
 		ppc440spe_setup_pcie_rootpoint(hose, i);
+
+		env = getenv ("pciscandelay");
+		if (env != NULL) {
+			delay = simple_strtoul (env, NULL, 10);
+			if (delay > 5)
+				printf ("Warning, expect noticable delay before PCIe"
+					"scan due to 'pciscandelay' value!\n");
+			mdelay (delay * 1000);
+		}
+
 		/*
 		 * Config access can only go down stream
 		 */
 		hose->last_busno = pci_hose_scan(hose);
+		bus = hose->last_busno + 1;
 #endif
 	}
 }
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 778aafc..7b16f8a 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -104,6 +104,13 @@ int checkboard(void)
 	return  0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+}
 
 /*************************************************************************
  *  int testdram()
@@ -161,7 +168,7 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init( struct pci_controller *hose )
 {
 	unsigned long strap;
@@ -179,7 +186,7 @@ int pci_pre_init( struct pci_controller *hose )
 
 	return  1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 
 /*************************************************************************
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 3f6d204..3bd1b81 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -306,7 +306,7 @@ long int fixed_sdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -323,7 +323,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
index 06ef7f9..e1c9ad4 100644
--- a/board/amcc/sequoia/Makefile
+++ b/board/amcc/sequoia/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o sdram.o
+COBJS	= $(BOARD).o cmd_sequoia.o sdram.o
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
new file mode 100644
index 0000000..f3803c0
--- /dev/null
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/*
+ * There are 2 versions of production Sequoia & Rainier platforms.
+ * The primary difference is the reference clock. Those with
+ * 33333333 reference clocks will also have 667MHz rated
+ * processors. Not enough differences to have unique clock
+ * settings.
+ *
+ * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
+ * values are independent of the rest of the clock settings.
+ *
+ * All Sequoias & Rainiers select from two possible EEPROMs in Boot
+ * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
+ * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
+ * the only  value affected for a 66MHz PCI and simply needs a +0x10.
+ */
+
+#define NAND_COMPATIBLE	0x01
+#define NOR_COMPATIBLE  0x02
+
+/* check with Stefan on CFG_I2C_EEPROM_ADDR */
+#define I2C_EEPROM_ADDR 0x52
+
+static char *config_labels[] = {
+	"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
+	"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
+	NULL
+};
+
+static u8 boot_configs[][17] = {
+	{
+		(NOR_COMPATIBLE),
+		0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+	}
+};
+
+/*
+ * Bytes 6,8,9,11 change for NAND boot
+ */
+static u8 nand_boot[] = {
+	0xd0,  0xa0, 0x68, 0x58
+};
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u8 *buf, bNAND;
+	int x, y, nbytes, selcfg;
+	extern char console_buffer[];
+
+	if (argc < 2) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if ((strcmp(argv[1], "nor") != 0) &&
+	    (strcmp(argv[1], "nand") != 0)) {
+		printf("Unsupported boot-device - only nor|nand support\n");
+		return 1;
+	}
+
+	/* set the nand flag based on provided input */
+	if ((strcmp(argv[1], "nand") == 0))
+		bNAND = 1;
+	else
+		bNAND = 0;
+
+	printf("Available configurations: \n\n");
+
+	if (bNAND) {
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+			/* filter on nand compatible */
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				printf(" %d - %s\n", (y+1), config_labels[x]);
+				y++;
+			}
+		}
+	} else {
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+			/* filter on nor compatible */
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
+				printf(" %d - %s\n", (y+1), config_labels[x]);
+				y++;
+			}
+		}
+	}
+
+	do {
+		nbytes = readline(" Selection [1-x / quit]: ");
+
+		if (nbytes) {
+			if (strcmp(console_buffer, "quit") == 0)
+				return 0;
+			selcfg = simple_strtol(console_buffer, NULL, 10);
+			if ((selcfg < 1) || (selcfg > y))
+				nbytes = 0;
+		}
+	} while (nbytes == 0);
+
+
+	y = (selcfg - 1);
+
+	for (x = 0; boot_configs[x][0] != 0; x++) {
+		if (bNAND) {
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		} else {
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		}
+	}
+
+	buf = &boot_configs[x][1];
+
+	if (bNAND) {
+		buf[6] = nand_boot[0];
+		buf[8] = nand_boot[1];
+		buf[9] = nand_boot[2];
+		buf[11] = nand_boot[3];
+	}
+
+	/* check CPLD register +5 for PCI 66MHz flag */
+	if (in8(CFG_BCSR_BASE + 5) & 0x01)
+		buf[5] += 0x10;
+
+	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
+		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
+	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+
+	printf("Done\n");
+	printf("Please power-cycle the board for the changes to take effect\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bootstrap,	2,	0,	do_bootstrap,
+	"bootstrap - program the I2C bootstrap EEPROM\n",
+	"<nand|nor> - strap to boot from NAND or NOR flash\n"
+	);
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 45bcd4b..5fe3af9 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -126,6 +126,9 @@ tlbtab:
 	/* TLB-entry for peripherals */
 	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
+	/* TLB-entry PCI IO Space - from sr@denx.de */
+	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
 	tlbtab_end
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index d045df1..78e2cb4 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -387,7 +387,11 @@ void denali_core_search_data_eye(unsigned long memory_size)
 long int initdram (int board_type)
 {
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_SPL)
 	ulong speed = get_bus_freq(0);
+#else
+	ulong speed = 133333333;	/* 133MHz is on the safe side	*/
+#endif
 
 	mtsdram(DDR0_02, 0x00000000);
 
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 930fa71..f823117 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -25,7 +25,6 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <ppc440.h>
-#include "sequoia.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -226,7 +225,7 @@ int misc_init_r(void)
 	if (act == NULL || strcmp(act, "hostdev") == 0)	{
 		/* SDR Setting */
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
-		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
 		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mfsdr(SDR0_USB2H0CR, usb2h0cr);
 
@@ -254,7 +253,7 @@ int misc_init_r(void)
 		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
 
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
-		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
@@ -298,7 +297,7 @@ int misc_init_r(void)
 		/* SDR Setting */
 		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mfsdr(SDR0_USB2H0CR, usb2h0cr);
-		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
@@ -323,7 +322,7 @@ int misc_init_r(void)
 
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
 
 		/*clear resets*/
@@ -363,8 +362,8 @@ int checkboard(void)
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = *(u8 *)(CFG_BCSR_BASE + 0);
-	val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
+	rev = in8(CFG_BCSR_BASE + 0);
+	val = in8(CFG_BCSR_BASE + 5) & 0x01;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {
@@ -426,23 +425,10 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
-#if 0
-	/*--------------------------------------------------------------------------+
-	 *	Cactus is always configured as the host & requires the
-	 *	PCI arbiter to be enabled ???
-	 *--------------------------------------------------------------------------*/
-	unsigned long strap;
-	mfsdr(sdr_sdstp1, strap);
-	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
-		printf("PCI: SDR0_STRP1[PAE] not set.\n");
-		printf("PCI: Configuration aborted.\n");
-		return 0;
-	}
-#endif
 
 	/*-------------------------------------------------------------------------+
 	  | Set priority for all PLB3 devices to 0.
@@ -480,7 +466,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
@@ -586,3 +572,13 @@ int is_pci_host(struct pci_controller *hose)
 	return (1);
 }
 #endif				/* defined(CONFIG_PCI) */
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h
deleted file mode 100644
index 1d44b16..0000000
--- a/board/amcc/sequoia/sequoia.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-/*----------------------------------------------------------------------------+
-  | EBC Configuration Register - EBC0_CFG
-  +----------------------------------------------------------------------------*/
-/* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
-/* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED	    0x00000000
-/* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK	    0x38000000
-#define EBC0_CFG_RTC_16PERCLK	    0x00000000
-#define EBC0_CFG_RTC_32PERCLK	    0x08000000
-#define EBC0_CFG_RTC_64PERCLK	    0x10000000
-#define EBC0_CFG_RTC_128PERCLK	    0x18000000
-#define EBC0_CFG_RTC_256PERCLK	    0x20000000
-#define EBC0_CFG_RTC_512PERCLK	    0x28000000
-#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
-#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
-/* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW	    0x00000000
-#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
-#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
-#define EBC0_CFG_EMPL_HIGH	    0x06000000
-/* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW	    0x00000000
-#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
-#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
-#define EBC0_CFG_EMPH_HIGH	    0x01800000
-/* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
-/* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW	    0x00000000
-#define EBC0_CFG_BPF_TWODW	    0x00100000
-#define EBC0_CFG_BPF_FOURDW	    0x00200000
-/* External Master Size */
-#define EBC0_CFG_EMS_8BIT	    0x00000000
-/* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED	    0x00000000
-#define EBC0_CFG_PME_ENABLED	    0x00020000
-/* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
-
-#define SDR0_USB0                    0x0320     /* USB Control Register */
diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile
new file mode 100644
index 0000000..9731c6e
--- /dev/null
+++ b/board/amcc/taihu/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o lcd.o update.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/taihu/config.mk b/board/amcc/taihu/config.mk
new file mode 100644
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/amcc/taihu/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c
new file mode 100644
index 0000000..290259e
--- /dev/null
+++ b/board/amcc/taihu/flash.c
@@ -0,0 +1,1083 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+#define CFG_FLASH_CHAR_SIZE unsigned char
+#define CFG_FLASH_CHAR_ADDR0 (0x0aaa)
+#define CFG_FLASH_CHAR_ADDR1 (0x0555)
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef FLASH_BASE1_PRELIM
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1=0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b0, size_b0 << 20);
+	}
+
+	if (size_b0) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+#endif
+		/* Also protect sector containing initial power-up instruction */
+		/* (flash_protect() checks address range - other call ignored) */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+
+		flash_info[0].size = size_b0;
+	}
+#ifdef FLASH_BASE1_PRELIM
+	size_b1 =
+	    flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2;
+
+	if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+		       size_b1, size_b1 << 20);
+	}
+
+	if (size_b1) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
+		flash_info[1].size = size_b1;
+	}
+#endif
+	return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000*2);
+		}
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000*2);
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
+
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMD016:
+		printf("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM033C:
+		printf("AM29LV033C (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMLV128U:
+		printf("AM29LV128U (128 Mbit * 2, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_STMW320DT:
+		printf ("M29W320DT (32 M, top sector)\n");
+		break;
+	case FLASH_S29GL128N:
+		printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+	       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef FLASH_BASE1_PRELIM
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	if ((ulong)addr == FLASH_BASE1_PRELIM) {
+		return flash_get_size_2(addr, info);
+	} else {
+		return flash_get_size_1(addr, info);
+	}
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return 0;	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+		info->flash_id += FLASH_AMD016;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return 0;	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+	else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000 * 2);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return info->size;
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return flash_erase_2(info, s_first, s_last);
+	} else {
+		return flash_erase_1(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_1(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return 0;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef FLASH_BASE1_PRELIM
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return write_word_2(info, dest, data);
+	} else {
+		return write_word_1(info, dest, data);
+	}
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return 2;
+	}
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	CFG_FLASH_CHAR_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+	addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+	addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+	udelay(1000);
+
+	value = (CFG_FLASH_CHAR_SIZE)addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return 0;		/* no or unknown flash */
+	}
+
+	value = (CFG_FLASH_CHAR_SIZE)addr2[2];	/* device ID */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D:
+		info->flash_id += FLASH_AMD016;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;			/* => 2 MB */
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;			/* => 4 MB */
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;			/* => 0.5 MB */
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;			/* => 0.5 MB */
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;			/* => 1 MB */
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;			/* => 1 MB */
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;			/* => 2 MB */
+
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;			/* => 2 MB */
+	case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR:
+		if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2
+				&& (CFG_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {
+			info->flash_id += FLASH_AMLV128U;
+			info->sector_count = 256;
+			info->size = 0x01000000;
+		} else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2
+				&& (CFG_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {
+			info->flash_id += FLASH_S29GL128N;
+			info->sector_count = 128;
+			info->size = 0x01000000;
+		}
+		else
+			info->flash_id = FLASH_UNKNOWN;
+		break;			/* => 2 MB */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return 0;		/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00020000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0;
+	return info->size;
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
+	       (CFG_FLASH_WORD_SIZE) 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) { /* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
+				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
+				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_2(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return 2;
+	}
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+		addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+		addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+#endif /* FLASH_BASE1_PRELIM */
diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c
new file mode 100644
index 0000000..3d042df
--- /dev/null
+++ b/board/amcc/taihu/lcd.c
@@ -0,0 +1,257 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define LCD_CMD_ADDR	0x50100002
+#define LCD_DATA_ADDR	0x50100003
+#define LCD_BLK_CTRL	CPLD_REG1_ADDR
+
+static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
+static int addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+	out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
+}
+
+static void lcd_putc(int val)
+{
+	int i = 100;
+	char addr;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	addr = in_8((u8 *) LCD_CMD_ADDR);
+	udelay(50);
+	if ((addr != 0) && (addr % 0x10 == 0)) {
+		addr_flag ^= 0x40;
+		out_8((u8 *) LCD_CMD_ADDR, addr_flag);
+	}
+
+	udelay(50);
+	out_8((u8 *) LCD_DATA_ADDR, val);
+	udelay(50);
+}
+
+static void lcd_puts(char *s)
+{
+	char *p = s;
+	int i = 100;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	while (*p)
+		lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+	int i = 100;
+	char *p = amcc_logo;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	out_8((u8 *) LCD_CMD_ADDR, 0x80);
+	while (*p)
+		lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+	puts("LCD: ");
+	out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
+	udelay(50);
+	out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
+	udelay(50);
+	out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
+	udelay(2000);
+	out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
+	udelay(50);
+	lcd_bl_ctrl(0x02);		/* set backlight on */
+	lcd_put_logo();
+	puts("ready\n");
+
+	return 0;
+}
+
+static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	out_8((u8 *) LCD_CMD_ADDR, 0x01);
+	udelay(2000);
+
+	return 0;
+}
+
+static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_puts(argv[1]);
+
+	return 0;
+}
+
+static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_putc((char)argv[1][0]);
+
+	return 0;
+}
+
+static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong count;
+	ulong dir;
+	char cur_addr;
+
+	if (argc < 3) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+
+	count = simple_strtoul(argv[1], NULL, 16);
+	if (count > 31) {
+		printf("unable to shift > 0x20\n");
+		count = 0;
+	}
+
+	dir = simple_strtoul(argv[2], NULL, 16);
+	cur_addr = in_8((u8 *) LCD_CMD_ADDR);
+	udelay(50);
+
+	if (dir == 0x0) {
+		if (addr_flag == 0x80) {
+			if (count >= (cur_addr & 0xf)) {
+				out_8((u8 *) LCD_CMD_ADDR, 0x80);
+				udelay(50);
+				count = 0;
+			}
+		} else {
+			if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+				out_8((u8 *) LCD_CMD_ADDR, 0x80);
+				addr_flag = 0x80;
+				udelay(50);
+				count = 0x0;
+			} else if (count >= ( cur_addr & 0xf)) {
+				count -= cur_addr & 0xf ;
+				out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
+				addr_flag = 0x80;
+				udelay(50);
+			}
+		}
+	} else {
+		if (addr_flag == 0x80) {
+			if (count >= (0x1f - (cur_addr & 0xf))) {
+				count = 0x0;
+				addr_flag = 0xc0;
+				out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
+				udelay(50);
+			} else if ((count + (cur_addr & 0xf ))>=  0x0f) {
+				count = count + (cur_addr & 0xf) - 0x0f;
+				addr_flag = 0xc0;
+				out_8((u8 *) LCD_CMD_ADDR, 0xc0);
+				udelay(50);
+			}
+		} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
+			count = 0x0;
+			out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
+			udelay(50);
+		}
+	}
+	while (count--) {
+		if (dir == 0)
+			out_8((u8 *) LCD_CMD_ADDR, 0x10);
+		else
+			out_8((u8 *) LCD_CMD_ADDR, 0x14);
+		udelay(50);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lcd_cls, 1, 1, do_lcd_clear,
+	"lcd_cls - lcd clear display\n",
+	NULL
+	);
+
+U_BOOT_CMD(
+	lcd_puts, 2, 1, do_lcd_puts,
+	"lcd_puts - display string on lcd\n",
+	"<string> - <string> to be displayed\n"
+	);
+
+U_BOOT_CMD(
+	lcd_putc, 2, 1, do_lcd_putc,
+	"lcd_putc - display char on lcd\n",
+	"<char> - <char> to be displayed\n"
+	);
+
+U_BOOT_CMD(
+	lcd_cur, 3, 1, do_lcd_cur,
+	"lcd_cur - shift cursor on lcd\n",
+	"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
+	" <count> - 0..31\n"
+	" <dir>   - 0=backward 1=forward\n"
+	);
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
new file mode 100644
index 0000000..ea83671
--- /dev/null
+++ b/board/amcc/taihu/taihu.c
@@ -0,0 +1,240 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <asm/gpio.h>
+
+extern int lcd_init(void);
+
+/*
+ * board_early_init_f
+ */
+int board_early_init_f(void)
+{
+	lcd_init();
+
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000000);
+	mtdcr(uicpr, 0xFFFF7F00);	/* set int polarities */
+	mtdcr(uictr, 0x00000000);	/* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+
+	mtebc(pb3ap, CFG_EBC_PB3AP);	/* memory bank 3 (CPLD_LCM) initialization */
+	mtebc(pb3cr, CFG_EBC_PB3CR);
+
+	/*
+	 * Configure CPC0_PCI to enable PerWE as output
+	 * and enable the internal PCI arbiter
+	 */
+	mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*************************************************************************
+ *  long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+	return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
+}
+
+static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+	char stat;
+	int i;
+
+	stat = in_8((u8 *) CPLD_REG0_ADDR);
+	printf("SW2 status: ");
+	for (i=0; i<4; i++) /* 4-position */
+		printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
+	printf("\n");
+	return 0;
+}
+
+U_BOOT_CMD (
+	sw2_stat, 1, 1, do_sw_stat,
+	"sw2_stat - show status of switch 2\n",
+	NULL
+	);
+
+static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+	int led_no;
+
+	if (argc != 3) {
+		printf("%s", cmd_tp->usage);
+		return -1;
+	}
+
+	led_no = simple_strtoul(argv[1], NULL, 16);
+	if (led_no != 1 && led_no != 2) {
+		printf("%s", cmd_tp->usage);
+		return -1;
+	}
+
+	if (strcmp(argv[2],"off") == 0x0) {
+		if (led_no == 1)
+			gpio_write_bit(30, 1);
+		else
+			gpio_write_bit(31, 1);
+	} else if (strcmp(argv[2],"on") == 0x0) {
+		if (led_no == 1)
+			gpio_write_bit(30, 0);
+		else
+			gpio_write_bit(31, 0);
+	} else {
+		printf("%s", cmd_tp->usage);
+		return -1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD (
+	led_ctl, 3, 1, do_led_ctl,
+	"led_ctl	- make led 1 or 2  on or off\n",
+	"<led_no> <on/off>	-  make led <led_no> on/off,\n"
+	"\tled_no is 1 or 2\t"
+	);
+
+#define SPI_CS_GPIO0	0
+#define SPI_SCLK_GPIO14	14
+#define SPI_DIN_GPIO15	15
+#define SPI_DOUT_GPIO16	16
+
+void spi_scl(int bit)
+{
+	gpio_write_bit(SPI_SCLK_GPIO14, bit);
+}
+
+void spi_sda(int bit)
+{
+	gpio_write_bit(SPI_DOUT_GPIO16, bit);
+}
+
+unsigned char spi_read(void)
+{
+	return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
+}
+
+void taihu_spi_chipsel(int cs)
+{
+	gpio_write_bit(SPI_CS_GPIO0, cs);
+}
+
+spi_chipsel_type spi_chipsel[]= {
+	taihu_spi_chipsel
+};
+
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+#ifdef CONFIG_PCI
+static unsigned char int_lines[32] = {
+	29, 30, 27, 28, 29, 30, 25, 27,
+	29, 30, 27, 28, 29, 30, 27, 28,
+	29, 30, 27, 28, 29, 30, 27, 28,
+	29, 30, 27, 28, 29, 30, 27, 28};
+
+static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+	hose->fixup_irq = taihu_pci_fixup_irq;
+	return 1;
+}
+#endif /* CONFIG_PCI */
+
+#ifdef CFG_DRAM_TEST
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+	unsigned long msr;
+	unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_EE));
+
+	for (k = 0; k < total_kbytes ;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0)
+			printf("%3d MB\r", k / 1024);
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	mtmsr(msr);
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST */
diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds
new file mode 100644
index 0000000..be03092
--- /dev/null
+++ b/board/amcc/taihu/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c
new file mode 100644
index 0000000..55ad535
--- /dev/null
+++ b/board/amcc/taihu/update.c
@@ -0,0 +1,132 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#define PCI_M66EN 0x10
+
+static uchar buf_33[] =
+{
+	0xb5,	/* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+	0x80,	/* 0x01~0x03:ptm1ms =0x80000001 */
+	0x00,
+	0x00,
+	0x00,	/* 0x04~0x06:ptm1la = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x07~0x09:ptm2ma = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x0a~0x0c:ptm2la = 0x00000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x0d~0x0e:vendor id 0x1014*/
+	0x14,
+	0x00,	/* 0x0f~0x10:device id 0x0000*/
+	0x00,
+	0x00,	/* 0x11:revision 0x00 */
+	0x00,	/* 0x12~0x14:class 0x000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x15~0x16:subsystem vendor id */
+	0xe8,
+	0x00,	/* 0x17~0x18:subsystem device id */
+	0x00,
+	0x61,	/* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+	0x68,	/* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+	0x2d,	/* 0x1b: fwdvb=0b101,fwdva=0b101 */
+	0x82,	/* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+	0xbe,	/* 0x1d: tun[24-31]=0xbe */
+	0x00,
+	0x00
+};
+
+static uchar buf_66[] =
+{
+	0xb5,	/* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+	0x80,	/* 0x01~0x03:ptm1ms =0x80000001 */
+	0x00,
+	0x00,
+	0x00,	/* 0x04~0x06:ptm1la = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x07~0x09:ptm2ma = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x0a~0x0c:ptm2la = 0x00000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x0d~0x0e:vendor id 0x1014*/
+	0x14,
+	0x00,	/* 0x0f~0x10:device id 0x0000*/
+	0x00,
+	0x00,	/* 0x11:revision 0x00 */
+	0x00,	/* 0x12~0x14:class 0x000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x15~0x16:subsystem vendor id */
+	0xe8,
+	0x00,	/* 0x17~0x18:subsystem device id */
+	0x00,
+	0x61,	/* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+	0x68,	/* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+	0x2d,	/* 0x1b: fwdvb=0b101,fwdva=0b101 */
+	0x82,	/* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+	0xbe,	/* 0x1d: tun[24-31]=0xbe */
+	0x00,
+	0x00
+};
+
+static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
+{
+	ulong len = 0x20;
+	uchar chip = CFG_I2C_EEPROM_ADDR;
+	uchar *pbuf;
+	uchar base;
+	int i;
+
+	if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
+		pbuf = buf_33;
+		base = 0x00;
+	} else {
+		pbuf = buf_66;
+		base = 0x40;
+	}
+
+	for (i = 0; i< len; i++, base++) {
+		if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
+			printf("i2c_write fail\n");
+			return 1;
+		}
+		udelay(11000);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD (
+	update_boot_eeprom, 1, 1, update_boot_eeprom,
+	"update_boot_eeprom  - update boot eeprom content\n",
+	NULL
+	);
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 1a2e53b..f00397e 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -32,6 +32,8 @@
 void show_reset_reg(void);
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int lcd_init(void);
 
 int board_early_init_f (void)
@@ -236,7 +238,7 @@ int testdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -253,7 +255,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
@@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index c2e12ba..912f09e 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -385,7 +385,7 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
@@ -426,7 +426,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index c92dcf7..67e8f8f 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -70,9 +70,9 @@ tlbtabA:
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -112,9 +112,9 @@ tlbtabB:
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 90eaab1..d7cc384 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -34,6 +34,8 @@
 #include "yucca.h"
 #include "../cpu/ppc4xx/440spe_pcie.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef PCIE_ENDPOINT
 /* #define PCIE_ENDPOINT 1 */
 
@@ -562,6 +564,40 @@ int checkboard (void)
 	return 0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+	if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+		return 1;
+	else
+		return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_WRDTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+	return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_CLKTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+	return default_val;
+}
+
 #if defined(CFG_DRAM_TEST)
 int testdram (void)
 {
@@ -604,7 +640,7 @@ int testdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -621,7 +657,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
@@ -634,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
@@ -812,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
 	struct pci_controller *hose;
 	int i, bus;
+	char *env;
+	unsigned int delay;
 
 	/*
 	 * assume we're called after the PCIX hose is initialized, which takes
 	 * bus ID 0 and therefore start numbering PCIe's from 1.
 	 */
-	bus = 1;
+	bus = busno;
 	for (i = 0; i <= 2; i++) {
 		/* Check for yucca card presence */
 		if (!yucca_pcie_card_present(i))
@@ -840,8 +876,8 @@ void pcie_setup_hoses(void)
 
 		hose = &pcie_hose[i];
 		hose->first_busno = bus;
-		hose->last_busno  = bus;
-		bus++;
+		hose->last_busno = bus;
+		hose->current_busno = bus;
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
@@ -861,10 +897,21 @@ void pcie_setup_hoses(void)
 		 */
 #else
 		ppc440spe_setup_pcie_rootpoint(hose, i);
+
+		env = getenv ("pciscandelay");
+		if (env != NULL) {
+			delay = simple_strtoul (env, NULL, 10);
+			if (delay > 5)
+				printf ("Warning, expect noticable delay before PCIe"
+					"scan due to 'pciscandelay' value!\n");
+			mdelay (delay * 1000);
+		}
+
 		/*
 		 * Config access can only go down stream
 		 */
 		hose->last_busno = pci_hose_scan(hose);
+		bus = hose->last_busno + 1;
 #endif
 	}
 }