Merge with /home/wd/git/u-boot/master

14 files changed, 3304 insertions, 20 deletions

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 7c98920..c93ba6e 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -435,7 +435,7 @@ long int initdram (int board_type)
 	 */
 	init_spd_array();
 
-	dram_size = spd_sdram (0);
+	dram_size = spd_sdram();
 
 	return dram_size;
 }
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
index 5f5fcde..1ce6366 100644
--- a/board/amcc/bamboo/bamboo.h
+++ b/board/amcc/bamboo/bamboo.h
@@ -283,10 +283,8 @@
 /*----------------------------------------------------------------------------+
   | PPC440EP GPIOs addresses.
   +----------------------------------------------------------------------------*/
-#define GPIO0_BASE	 0xEF600B00
 #define GPIO0_REAL	 0xEF600B00
 
-#define GPIO1_BASE	 0xEF600C00
 #define GPIO1_REAL	 0xEF600C00
 
 /* Offsets */
@@ -332,17 +330,6 @@
 
 
 /*----------------------------------------------------------------------------+
-  | Declare Configuration values
-  +----------------------------------------------------------------------------*/
-typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
-typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
-
-typedef struct { unsigned long	add;	/* gpio core base address */
-	gpio_driver_t  in_out; /* Driver Setting */
-	gpio_select_t  alt_nb; /* Selected Alternate */
-} gpio_param_s;
-
-/*----------------------------------------------------------------------------+
   |			XX     XX
   |
   | XXXXXX   XXX XX    XXX    XXX
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
index 35cb655..9d7f4c3 100644
--- a/board/amcc/bamboo/config.mk
+++ b/board/amcc/bamboo/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFA0000
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index 86d0db7..92dc9d4 100644
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -313,13 +313,13 @@ void sdram_init(void)
 	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
 	mtsdram(mem_rtr, 0x04080000);	/* ?? */
 	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
-	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
+	mtsdram(mem_cfg0, 0x30000000);	/* Disable EEC */
 	udelay(400);		/* Delay 200 usecs (min)            */
 
 	/*--------------------------------------------------------------------
 	 * Enable the controller, then wait for DCEN to complete
 	 *------------------------------------------------------------------*/
-	mtsdram(mem_cfg0, 0x84000000);	/* Enable */
+	mtsdram(mem_cfg0, 0x80000000);	/* Enable */
 
 	for (;;) {
 		mfsdram(mem_mcsts, reg);
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 6742441..7f2e718 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -309,13 +309,13 @@ void sdram_init(void)
 	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
 	mtsdram(mem_rtr, 0x04080000);	/* ?? */
 	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
-	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
+	mtsdram(mem_cfg0, 0x30000000);	/* Disable EEC */
 	udelay(400);		/* Delay 200 usecs (min)            */
 
 	/*--------------------------------------------------------------------
 	 * Enable the controller, then wait for DCEN to complete
 	 *------------------------------------------------------------------*/
-	mtsdram(mem_cfg0, 0x84000000);	/* Enable */
+	mtsdram(mem_cfg0, 0x80000000);	/* Enable */
 
 	for (;;) {
 		mfsdram(mem_mcsts, reg);
diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile
new file mode 100644
index 0000000..c85fa31
--- /dev/null
+++ b/board/amcc/yucca/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o cmd_yucca.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
new file mode 100644
index 0000000..e698b20
--- /dev/null
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -0,0 +1,288 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for evb440spe
+ */
+
+#include <common.h>
+#include <command.h>
+#include "yucca.h"
+#include <i2c.h>
+#include <asm/byteorder.h>
+
+extern void print_evb440spe_info(void);
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
+		int flag, int argc, char *argv[]);
+
+extern int cmd_get_data_size(char* arg, int default_size);
+
+/* ------------------------------------------------------------------------- */
+int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	return setBootStrapClock (cmdtp, 1, flag, argc, argv);
+}
+
+/* ------------------------------------------------------------------------- */
+/* Modify memory.
+ *
+ * Syntax:
+ *	evb440spe wrclk prom0,prom1
+ */
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
+		int argc, char *argv[])
+{
+	uchar	chip;
+	ulong	data;
+	int	nbytes;
+	extern char console_buffer[];
+
+	char sysClock[4];
+	char cpuClock[4];
+	char plbClock[4];
+	char pcixClock[4];
+
+	if (argc < 3) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (strcmp(argv[2], "prom0") == 0)
+		chip = IIC0_BOOTPROM_ADDR;
+	else
+		chip = IIC0_ALT_BOOTPROM_ADDR;
+
+	do {
+		printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if ((strcmp(console_buffer, "33") != 0) &
+				(strcmp(console_buffer, "66") != 0))
+			nbytes=0;
+
+		strcpy(sysClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	do {
+		if (strcmp(sysClock, "66") == 0) {
+			printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
+		} else {
+#ifdef	CONFIG_STRESS
+			printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
+#else
+			printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
+#endif
+		}
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if (strcmp(sysClock, "66") == 0) {
+			if ((strcmp(console_buffer, "400") != 0) &
+					(strcmp(console_buffer, "533") != 0)
+#ifdef	CONFIG_STRESS
+					& (strcmp(console_buffer, "667") != 0)
+#endif
+			   ) {
+				nbytes = 0;
+			}
+		} else {
+			if ((strcmp(console_buffer, "400") != 0) &
+					(strcmp(console_buffer, "500") != 0) &
+					(strcmp(console_buffer, "533") != 0)
+#ifdef	CONFIG_STRESS
+					& (strcmp(console_buffer, "667") != 0)
+#endif
+			   ) {
+				nbytes = 0;
+			}
+		}
+
+		strcpy(cpuClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	if (strcmp(cpuClock, "500") == 0){
+		strcpy(plbClock, "166");
+	} else if (strcmp(cpuClock, "533") == 0){
+		strcpy(plbClock, "133");
+	} else {
+		do {
+			if (strcmp(cpuClock, "400") == 0)
+				printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n");
+
+#ifdef	CONFIG_STRESS
+			if (strcmp(cpuClock, "667") == 0)
+				printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n");
+
+#endif
+			nbytes = readline (" ? ");
+
+			if (strcmp(console_buffer, "quit") == 0)
+				return 0;
+
+			if (strcmp(cpuClock, "400") == 0) {
+				if ((strcmp(console_buffer, "100") != 0) &
+						(strcmp(console_buffer, "133") != 0))
+					nbytes = 0;
+			}
+#ifdef	CONFIG_STRESS
+			if (strcmp(cpuClock, "667") == 0) {
+				if ((strcmp(console_buffer, "133") != 0) &
+						(strcmp(console_buffer, "166") != 0))
+					nbytes = 0;
+			}
+#endif
+			strcpy(plbClock, console_buffer);
+
+		} while (nbytes == 0);
+	}
+
+	do {
+		printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n");
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if ((strcmp(console_buffer, "33") != 0) &
+				(strcmp(console_buffer, "66") != 0) &
+				(strcmp(console_buffer, "100") != 0) &
+				(strcmp(console_buffer, "133") != 0)) {
+			nbytes = 0;
+		}
+		strcpy(pcixClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	printf("\nsys clk   = %sMhz\n", sysClock);
+	printf("cpu clk   = %sMhz\n", cpuClock);
+	printf("plb clk   = %sMhz\n", plbClock);
+	printf("Pci-X clk = %sMhz\n", pcixClock);
+
+	do {
+		printf("\npress [y] to write I2C bootstrap \n");
+		printf("or [n] to abort.  \n");
+		printf("Don't forget to set board switches \n");
+		printf("according to your choice before re-starting \n");
+		printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+
+		nbytes = readline (" ? ");
+		if (strcmp(console_buffer, "n") == 0)
+			return 0;
+
+	} while (nbytes == 0);
+
+	if (strcmp(sysClock, "33") == 0) {
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "100") == 0))
+			data = 0x8678c206;
+
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x8678c2c6;
+
+		if ((strcmp(cpuClock, "500") == 0))
+			data = 0x8778f2c6;
+
+		if ((strcmp(cpuClock, "533") == 0))
+			data = 0x87790252;
+
+#ifdef	CONFIG_STRESS
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x87794256;
+
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "166") == 0))
+			data = 0x87794206;
+
+#endif
+	}
+	if (strcmp(sysClock, "66") == 0) {
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "100") == 0))
+			data = 0x84706206;
+
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x847062c6;
+
+		if ((strcmp(cpuClock, "533") == 0))
+			data = 0x85708206;
+
+#ifdef	CONFIG_STRESS
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x8570a256;
+
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "166") == 0))
+			data = 0x8570a206;
+
+#endif
+	}
+
+#ifdef	DEBUG
+	printf(" pin strap0 to write in i2c  = %x\n", data);
+#endif	/* DEBUG */
+
+	if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
+		printf("Error writing strap0 in %s\n", argv[2]);
+
+	if (strcmp(pcixClock, "33") == 0)
+		data = 0x00000701;
+
+	if (strcmp(pcixClock, "66") == 0)
+		data = 0x00000601;
+
+	if (strcmp(pcixClock, "100") == 0)
+		data = 0x00000501;
+
+	if (strcmp(pcixClock, "133") == 0)
+		data = 0x00000401;
+
+	if (strcmp(plbClock, "166") == 0)
+		data = data | 0x05950000;
+	else
+		data = data | 0x05A50000;
+
+#ifdef	DEBUG
+	printf(" pin strap1 to write in i2c  = %x\n", data);
+#endif	/* DEBUG */
+
+	udelay(1000);
+	if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
+		printf("Error writing strap1 in %s\n", argv[2]);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	evb440spe,	3,	1,	do_evb440spe,
+	"evb440spe - program the serial device strap\n",
+	"wrclk [prom0|prom1] - program the serial device strap\n"
+);
diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk
new file mode 100644
index 0000000..ff454eb
--- /dev/null
+++ b/board/amcc/yucca/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440SPe Reference Platform (yucca) board
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xfffb0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
new file mode 100644
index 0000000..15b8a46
--- /dev/null
+++ b/board/amcc/yucca/flash.c
@@ -0,0 +1,1054 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "yucca.h"
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+	{0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */
+	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
+	{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
+	{0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+	{0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+	{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
+	{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
+	{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
+	{0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			printf("AMD ");
+			break;
+		case FLASH_MAN_STM:
+			printf("STM ");
+			break;
+		case FLASH_MAN_FUJ:
+			printf("FUJITSU ");
+			break;
+		case FLASH_MAN_SST:
+			printf("SST ");
+			break;
+		case FLASH_MAN_MX:
+			printf("MIXC ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			printf("AM29F040 (512 Kbit, uniform sector size)\n");
+			break;
+		case FLASH_AM400B:
+			printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM400T:
+			printf("AM29LV400T (4 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AM800B:
+			printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM800T:
+			printf("AM29LV800T (8 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AMD016:
+			printf("AM29F016D (16 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_AM160B:
+			printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM160T:
+			printf("AM29LV160T (16 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AM320B:
+			printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM320T:
+			printf("AM29LV320T (32 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AM033C:
+			printf("AM29LV033C (32 Mbit, top boot sector)\n");
+			break;
+		case FLASH_SST800A:
+			printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_SST160A:
+			printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_STMW320DT:
+			printf ("M29W320DT (32 M, top sector)\n");
+			break;
+		case FLASH_MXLV320T:
+			printf ("MXLV320T (32 Mbit, top sector)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+			info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1)
+		return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+	else
+		return flash_get_size_1(addr, info);
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+			info->flash_id = FLASH_MAN_SST;
+			break;
+		case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+			info->flash_id = FLASH_MAN_STM;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x0080000;	/* => 512 ko */
+			break;
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x0080000;	/* => 512 ko */
+			break;
+
+		case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x0080000;	/* => 512 ko */
+			break;
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+			info->flash_id += FLASH_AMD016;
+			info->sector_count = 32;
+			info->size = 0x00200000;
+			break;		/* => 2 MB              */
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+			info->flash_id += FLASH_AMDLV033C;
+			info->sector_count = 64;
+			info->size = 0x00400000;
+			break;		/* => 4 MB              */
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+			info->flash_id += FLASH_AM400T;
+			info->sector_count = 11;
+			info->size = 0x00080000;
+			break;		/* => 0.5 MB            */
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+			info->flash_id += FLASH_AM400B;
+			info->sector_count = 11;
+			info->size = 0x00080000;
+			break;		/* => 0.5 MB            */
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00100000;
+			break;		/* => 1 MB              */
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00100000;
+			break;		/* => 1 MB              */
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00200000;
+			break;		/* => 2 MB              */
+
+		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00200000;
+			break;		/* => 2 MB              */
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+			(CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+		return flash_erase_2(info, s_first, s_last);
+	} else {
+		return flash_erase_1(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!", prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_1(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < 4; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i)
+			data = (data << 8) | *src++;
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *) cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+		return write_word_2(info, dest, data);
+	} else {
+		return write_word_1(info, dest, data);
+	}
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i, flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef  CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	int n;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+			info->flash_id = FLASH_MAN_SST;
+			break;
+		case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+			info->flash_id = FLASH_MAN_STM;
+			break;
+		case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+			info->flash_id = FLASH_MAN_MX;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+			info->flash_id += FLASH_STMW320DT;
+			info->sector_count = 67;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+			info->flash_id += FLASH_MXLV320T;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		/*  1 x 16k boot sector */
+		base -= 16 << 10;
+		--i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n = 0; n < 2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		/*  1 x 32k boot sector */
+		base -= 32 << 10;
+		--i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000a000;
+		info->start[i--] = base + info->size - 0x0000c000;
+		info->start[i--] = base + info->size - 0x0000e000;
+		info->start[i--] = base + info->size - 0x00010000;
+
+		for (; i >= 0; i--)
+			info->start[i] = base + i * 0x00010000;
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+
+			for (i = 4; i < info->sector_count; i++)
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+
+			for (; i >= 0; i--)
+				info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+			(CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!",	prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_2(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+	unsigned long val;
+	unsigned long ebc_boot_size;
+	unsigned long boot_selection;
+
+	mfsdr(sdr_pstrp0, val);
+	index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28;
+
+	if ((index == 0xc) || (index == 8)) {
+		/*
+		 * Boot Settings in IIC EEprom address 0xA8 or 0xA0
+		 * Read Serial Device Strap Register1 in PPC440SPe
+		 */
+		mfsdr(sdr_sdstp1, val);
+		boot_selection  = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+		ebc_boot_size   = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+		switch(boot_selection) {
+			case SDR0_SDSTP1_BOOT_SEL_EBC:
+				switch(ebc_boot_size) {
+					case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+						index = 3;
+						break;
+					case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+						index = 0;
+						break;
+				}
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_PCI:
+				index = 1;
+				break;
+
+		}
+	} /*else if (index == 0) {*/
+/*		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
+/*			index = 8;*/ /* sram below op code flash -> new index 8*/
+/*	}*/
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0)
+			continue;
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				&flash_info[i]);
+
+		flash_info[i].size = size_b[i];
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+					i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
new file mode 100644
index 0000000..cb28936
--- /dev/null
+++ b/board/amcc/yucca/init.S
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* port to AMCC 440SPE evaluatioon board - SG April 12,2005  */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	0x00000000
+#define SZ_4K	0x00000010
+#define SZ_16K	0x00000020
+#define SZ_64K	0x00000030
+#define SZ_256K	0x00000040
+#define SZ_1M	0x00000050
+#define SZ_16M	0x00000070
+#define SZ_256M	0x00000090
+
+/* Storage attributes */
+#define SA_W	0x00000800	/* Write-through */
+#define SA_I	0x00000400	/* Caching inhibited */
+#define SA_M	0x00000200	/* Memory coherence */
+#define SA_G	0x00000100	/* Guarded */
+#define SA_E	0x00000080	/* Endian */
+
+/* Access control */
+#define AC_X	0x00000024	/* Execute */
+#define AC_W	0x00000012	/* Write */
+#define AC_R	0x00000009	/* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	((EPN((epn)) | (sz) | TLB_VALID ))
+#define TLB1(rpn,erpn)	(((rpn) & 0xfffffc00) | (erpn))
+#define TLB2(a)		((a) & 0x00000fbf)
+
+#define tlbtab_start\
+	mflr	r1	;\
+	bl	0f	;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;\
+0:	mflr	r0	;\
+	mtlr	r1	;\
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
+
+	tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+
+	tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end
diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds
new file mode 100644
index 0000000..9df4f92
--- /dev/null
+++ b/board/amcc/yucca/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o		(.text)
+    board/amcc/yucca/init.o	(.text)
+    cpu/ppc4xx/kgdb.o		(.text)
+    cpu/ppc4xx/traps.o		(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o		(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/yucca/u-boot.lds.debug b/board/amcc/yucca/u-boot.lds.debug
new file mode 100644
index 0000000..474f922
--- /dev/null
+++ b/board/amcc/yucca/u-boot.lds.debug
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o		(.text)
+    board/amcc/yucca/init.o	(.text)
+    cpu/ppc4xx/kgdb.o		(.text)
+    cpu/ppc4xx/traps.o		(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o		(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
new file mode 100644
index 0000000..ce1312c
--- /dev/null
+++ b/board/amcc/yucca/yucca.c
@@ -0,0 +1,1096 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Port to AMCC-440SPE Evaluation Board SOP - April 2005
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include "yucca.h"
+
+void fpga_init (void);
+
+void get_sys_info(PPC440_SYS_INFO *board_cfg );
+int compare_to_true(char *str );
+char *remove_l_w_space(char *in_str );
+char *remove_t_w_space(char *in_str );
+int get_console_port(void);
+unsigned long ppcMfcpr(unsigned long cpr_reg);
+unsigned long ppcMfsdr(unsigned long sdr_reg);
+
+#define DEBUG_ENV
+#ifdef DEBUG_ENV
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+#define FALSE	0
+#define TRUE	1
+
+int board_early_init_f (void)
+{
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+#define BOOT_FROM_SMALL_FLASH		0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
+#define BOOT_FROM_PCI			0x02
+#define BOOT_DEVICE_UNKNOWN		0x03
+
+/*----------------------------------------------------------------------------+
+| EBC Devices Characteristics
+|   Peripheral Bank Access Parameters       -   EBC_BxAP
+|   Peripheral Bank Configuration Register  -   EBC_BxCR
++----------------------------------------------------------------------------*/
+
+/*
+ * Small Flash and FRAM
+ * BU Value
+ * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_SMALL_FLASH		EBC_BXAP_BME_DISABLED	| \
+					EBC_BXAP_TWT_ENCODE(7)	| \
+					EBC_BXAP_BCE_DISABLE	| \
+					EBC_BXAP_BCT_2TRANS	| \
+					EBC_BXAP_CSN_ENCODE(0)	| \
+					EBC_BXAP_OEN_ENCODE(0)	| \
+					EBC_BXAP_WBN_ENCODE(0)	| \
+					EBC_BXAP_WBF_ENCODE(0)	| \
+					EBC_BXAP_TH_ENCODE(0)	| \
+					EBC_BXAP_RE_DISABLED	| \
+					EBC_BXAP_SOR_DELAYED	| \
+					EBC_BXAP_BEM_WRITEONLY	| \
+					EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_SMALL_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SMALL_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xe7000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_8BIT
+
+/*
+ * Large Flash and SRAM
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_LARGE_FLASH		EBC_BXAP_BME_DISABLED	| \
+					EBC_BXAP_TWT_ENCODE(7)	| \
+					EBC_BXAP_BCE_DISABLE	| \
+					EBC_BXAP_BCT_2TRANS	| \
+					EBC_BXAP_CSN_ENCODE(0)	| \
+					EBC_BXAP_OEN_ENCODE(0)	| \
+					EBC_BXAP_WBN_ENCODE(0)	| \
+					EBC_BXAP_WBF_ENCODE(0)	| \
+					EBC_BXAP_TH_ENCODE(0)	| \
+					EBC_BXAP_RE_DISABLED	| \
+					EBC_BXAP_SOR_DELAYED	| \
+					EBC_BXAP_BEM_WRITEONLY	| \
+					EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_LARGE_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xE7000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_16BIT
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA			EBC_BXAP_BME_DISABLED	| \
+					EBC_BXAP_TWT_ENCODE(11)	| \
+					EBC_BXAP_BCE_DISABLE	| \
+					EBC_BXAP_BCT_2TRANS	| \
+					EBC_BXAP_CSN_ENCODE(10)	| \
+					EBC_BXAP_OEN_ENCODE(1)	| \
+					EBC_BXAP_WBN_ENCODE(1)	| \
+					EBC_BXAP_WBF_ENCODE(1)	| \
+					EBC_BXAP_TH_ENCODE(1)	| \
+					EBC_BXAP_RE_DISABLED	| \
+					EBC_BXAP_SOR_DELAYED	| \
+					EBC_BXAP_BEM_RW		| \
+					EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_FPGA_CS1		EBC_BXCR_BAS_ENCODE(0xe2000000)	| \
+					EBC_BXCR_BS_1MB			| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_16BIT
+
+	 unsigned long mfr;
+	/*
+	 * Define Variables for EBC initialization depending on BOOTSTRAP option
+	 */
+	unsigned long sdr0_pinstp, sdr0_sdstp1 ;
+	unsigned long bootstrap_settings, ebc_data_width, boot_selection;
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*-------------------------------------------------------------------+
+	 | Initialize EBC CONFIG -
+	 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+	 | default value :
+	 |	0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+	 |
+	 +-------------------------------------------------------------------*/
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+			EBC_CFG_PTD_ENABLE |
+			EBC_CFG_RTC_16PERCLK |
+			EBC_CFG_ATC_PREVIOUS |
+			EBC_CFG_DTC_PREVIOUS |
+			EBC_CFG_CTC_PREVIOUS |
+			EBC_CFG_OEO_PREVIOUS |
+			EBC_CFG_EMC_DEFAULT |
+			EBC_CFG_PME_DISABLE |
+			EBC_CFG_PR_16);
+
+	/*-------------------------------------------------------------------+
+	 |
+	 |  PART 1 : Initialize EBC Bank 1
+	 |  ==============================
+	 | Bank1 is always associated to the EPLD.
+	 | It has to be initialized prior to other banks settings computation
+	 | since some board registers values may be needed to determine the
+	 | boot type
+	 |
+	 +-------------------------------------------------------------------*/
+	mtebc(pb1ap, EBC_BXAP_FPGA);
+	mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
+
+	/*-------------------------------------------------------------------+
+	 |
+	 |  PART 2 : Determine which boot device was selected
+	 |  =================================================
+	 |
+	 |  Read Pin Strap Register in PPC440SPe
+	 |  Result can either be :
+	 |   - Boot strap = boot from EBC 8bits     => Small Flash
+	 |   - Boot strap = boot from PCI
+	 |   - Boot strap = IIC
+	 |  In case of boot from IIC, read Serial Device Strap Register1
+	 |
+	 |  Result can either be :
+	 |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
+	 |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
+	 |   - Boot from PCI
+	 |
+	 +-------------------------------------------------------------------*/
+	/* Read Pin Strap Register in PPC440SP */
+	sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
+	bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
+
+	switch (bootstrap_settings) {
+		case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
+			/*
+			 * Strapping Option A
+			 * Boot from EBC - 8 bits , Small Flash
+			 */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+		case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
+			/*
+			 * Strappping Option B
+			 * Boot from PCI
+			 */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+		case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
+		case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
+			/*
+			 * Strapping Option C or D
+			 * Boot Settings in IIC EEprom address 0x50 or 0x54
+			 * Read Serial Device Strap Register1 in PPC440SPe
+			 */
+			sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
+			boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
+			ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
+
+			switch (boot_selection) {
+				case SDR0_SDSTP1_ERPN_EBC:
+					switch (ebc_data_width) {
+						case SDR0_SDSTP1_EBCW_16_BITS:
+							computed_boot_device =
+								BOOT_FROM_LARGE_FLASH_OR_SRAM;
+							break;
+						case SDR0_SDSTP1_EBCW_8_BITS :
+							computed_boot_device = BOOT_FROM_SMALL_FLASH;
+							break;
+					}
+					break;
+
+				case SDR0_SDSTP1_ERPN_PCI:
+					computed_boot_device = BOOT_FROM_PCI;
+					break;
+				default:
+					/* should not occure */
+					computed_boot_device = BOOT_DEVICE_UNKNOWN;
+			}
+			break;
+		default:
+			/* should not be */
+			computed_boot_device = BOOT_DEVICE_UNKNOWN;
+			break;
+	}
+
+	/*-------------------------------------------------------------------+
+	 |
+	 |  PART 3 : Compute EBC settings depending on selected boot device
+	 |  ======   ======================================================
+	 |
+	 | Resulting EBC init will be among following configurations :
+	 |
+	 |  - Boot from EBC 8bits => boot from Small Flash selected
+	 |            EBC-CS0     = Small Flash
+	 |            EBC-CS2     = Large Flash and SRAM
+	 |
+	 |  - Boot from EBC 16bits => boot from Large Flash or SRAM
+	 |            EBC-CS0     = Large Flash or SRAM
+	 |            EBC-CS2     = Small Flash
+	 |
+	 |  - Boot from PCI
+	 |            EBC-CS0     = not initialized to avoid address contention
+	 |            EBC-CS2     = same as boot from Small Flash selected
+	 |
+	 +-------------------------------------------------------------------*/
+	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+	switch (computed_boot_device) {
+		/*-------------------------------------------------------------------*/
+		case BOOT_FROM_PCI:
+		/*-------------------------------------------------------------------*/
+			/*
+			 * By Default CS2 is affected to LARGE Flash
+			 * do not initialize SMALL FLASH to avoid address contention
+			 * Large Flash
+			 */
+			ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
+			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+			break;
+
+		/*-------------------------------------------------------------------*/
+		case BOOT_FROM_SMALL_FLASH:
+		/*-------------------------------------------------------------------*/
+			ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
+			ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
+
+			/*
+			 * Large Flash or SRAM
+			 */
+			/* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
+			ebc0_cs2_bxap_value = 0x048ff240;
+			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+			break;
+
+		/*-------------------------------------------------------------------*/
+		case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+		/*-------------------------------------------------------------------*/
+			ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
+			ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
+
+			/* Small flash */
+			ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
+			ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
+			break;
+
+		/*-------------------------------------------------------------------*/
+		default:
+		/*-------------------------------------------------------------------*/
+			/* BOOT_DEVICE_UNKNOWN */
+			break;
+	}
+
+	mtebc(pb0ap, ebc0_cs0_bxap_value);
+	mtebc(pb0cr, ebc0_cs0_bxcr_value);
+	mtebc(pb2ap, ebc0_cs2_bxap_value);
+	mtebc(pb2cr, ebc0_cs2_bxcr_value);
+
+	/*--------------------------------------------------------------------+
+	 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
+	 +--------------------------------------------------------------------+
+	+---------------------------------------------------------------------+
+	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
+	+---------+-----------------------------------+-------+-------+-------+
+	| IRQ 00  | UART0                             | High  | Level | Non   |
+	| IRQ 01  | UART1                             | High  | Level | Non   |
+	| IRQ 02  | IIC0                              | High  | Level | Non   |
+	| IRQ 03  | IIC1                              | High  | Level | Non   |
+	| IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
+	| IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
+	| IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
+	| IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
+	| IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
+	| IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
+	| IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
+	| IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
+	| IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
+	| IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
+	| IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
+	| IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
+	| IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
+	| IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
+	| IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
+	| IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+	| IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+	| IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+	| IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+	| IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
+	| IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
+	| IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
+	| IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
+	| IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
+	| IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
+	| IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
+	| IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
+	| IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
+	|----------------------------------------------------------------------
+	| IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 33  | MAL Serr                          | High  | Level | Non   |
+	| IRQ 34  | MAL Txde                          | High  | Level | Non   |
+	| IRQ 35  | MAL Rxde                          | High  | Level | Non   |
+	| IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
+	| IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
+	| IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
+	| IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
+	| IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
+	| IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
+	| IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
+	| IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
+	| IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
+	| IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
+	| IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
+	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
+	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
+	| IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 54  | DMA Error                         | High  | Level | Non   |
+	| IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
+	| IRQ 56  | Serial ROM                        | High  | Level | Non   |
+	| IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
+	| IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
+	| IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
+	| IRQ 62  | Reserved                          | High  | Level | Non   |
+	| IRQ 63  | XOR                               | High  | Level | Non   |
+	|----------------------------------------------------------------------
+	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
+	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
+	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
+	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
+	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
+	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
+	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
+	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
+	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
+	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
+	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
+	|---------------------------------------------------------------------
+	| IRQ 96  | PE0 INTA                          | High  | Level | Non   |
+	| IRQ 97  | PE0 INTB                          | High  | Level | Non   |
+	| IRQ 98  | PE0 INTC                          | High  | Level | Non   |
+	| IRQ 99  | PE0 INTD                          | High  | Level | Non   |
+	| IRQ 100 | PE1 INTA                          | High  | Level | Non   |
+	| IRQ 101 | PE1 INTB                          | High  | Level | Non   |
+	| IRQ 102 | PE1 INTC                          | High  | Level | Non   |
+	| IRQ 103 | PE1 INTD                          | High  | Level | Non   |
+	| IRQ 104 | PE2 INTA                          | High  | Level | Non   |
+	| IRQ 105 | PE2 INTB                          | High  | Level | Non   |
+	| IRQ 106 | PE2 INTC                          | High  | Level | Non   |
+	| IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
+	| IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
+	| IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
+	| IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
+	| IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
+	| IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
+	| IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
+	| IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
+	| IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
+	| IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
+	| IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
+	| IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
+	| IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
+	| IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
+	| IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
+	| IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
+	| IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
+	| IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
+	| IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
+	| IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
+	| IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
+	+---------+-----------------------------------+-------+-------+------*/
+	/*--------------------------------------------------------------------+
+	 | Put UICs in PowerPC440SPemode.
+	 | Initialise UIC registers.  Clear all interrupts.  Disable all
+	 | interrupts.
+	 | Set critical interrupt values.  Set interrupt polarities.  Set
+	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 | interrupts again.
+	 +-------------------------------------------------------------------*/
+	mtdcr (uic3sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (uic3er, 0x00000000);	/* disable all interrupts */
+	mtdcr (uic3cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (uic3pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr (uic3vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (uic3sr, 0x00000000);	/* clear all  interrupts */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all  interrupts */
+
+	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (uic2er, 0x00000000);	/* disable all interrupts */
+	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (uic2pr, 0xebebebff);	/* Set Interrupt Polarities */
+	mtdcr (uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (uic1er, 0x00000000);	/* disable all interrupts */
+	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (uic1tr, 0x001f8040);	/* Set Interrupt Trigger Levels */
+	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (uic0er, 0x00000000);	/* disable all interrupts excepted
+					 * cascade to be checked */
+	mtdcr (uic0cr, 0x00104001);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (uic0pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (uic0tr, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts */
+
+	/* SDR0_MFR should be part of Ethernet init */
+	mfsdr (sdr_mfr, mfr);
+	mfr &= ~SDR0_MFR_ECS_MASK;
+	/*mtsdr(sdr_mfr, mfr);*/
+	fpga_init();
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Yucca - AMCC 440SPe Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+static long int yucca_probe_for_dimms(void)
+{
+	long int 	dimm_installed[MAXDIMMS];
+	long int	dimm_num, probe_result;
+	long int	dimms_found = 0;
+	uchar		dimm_addr = IIC0_DIMM0_ADDR;
+
+	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
+		/* check if there is a chip at the dimm address	*/
+		switch (dimm_num) {
+			case 0:
+				dimm_addr = IIC0_DIMM0_ADDR;
+				break;
+			case 1:
+				dimm_addr = IIC0_DIMM1_ADDR;
+				break;
+		}
+		probe_result = i2c_probe(dimm_addr);
+
+		if (probe_result == 0) {
+			dimm_installed[dimm_num] = TRUE;
+			dimms_found++;
+			debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num);
+		} else {
+			dimm_installed[dimm_num] = FALSE;
+			debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
+		}
+	}
+
+	if (dimms_found == 0) {
+		printf("ERROR - No memory installed.  Install a DDR-SDRAM DIMM.\n\n");
+		hang();
+	}
+
+	if (dimm_installed[0] != TRUE) {
+		printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
+		printf("        Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
+		hang();
+	}
+
+	return dimms_found;
+}
+
+/*************************************************************************
+ * init SDRAM controller with fixed value
+ * the initialization values are for 2x MICRON DDR2
+ * PN: MT18HTF6472DY-53EB2
+ * 512MB, DDR2, 533, CL4, ECC, REG
+ ************************************************************************/
+static long int fixed_sdram(void)
+{
+	long int yucca_dimms = 0;
+
+	yucca_dimms = yucca_probe_for_dimms();
+
+	/* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT	*/
+	mtdcr( 0x10, 0x00000021 );
+	mtdcr( 0x11, 0x84000000 );
+
+	/* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2	*/
+	mtdcr( 0x10, 0x00000020 );
+	mtdcr( 0x11, 0x2D122000 );
+
+	/* SET MCIF0_CODT   Die Termination On	*/
+	mtdcr( 0x10, 0x00000026 );
+	if (yucca_dimms == 2)
+		mtdcr( 0x11, 0x2A800021 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x11, 0x02800021 );
+
+	/* On-Die Termination for Bank 0	*/
+	mtdcr( 0x10, 0x00000022 );
+	if (yucca_dimms == 2)
+		mtdcr( 0x11, 0x18000000 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x11, 0x06000000 );
+
+	/*	On-Die Termination for Bank 1	*/
+	mtdcr( 0x10, 0x00000023 );
+	if (yucca_dimms == 2)
+		mtdcr( 0x11, 0x18000000 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x11, 0x01800000 );
+
+	/*	On-Die Termination for Bank 2	*/
+	mtdcr( 0x10, 0x00000024 );
+	if (yucca_dimms == 2)
+		mtdcr( 0x11, 0x01800000 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x11, 0x00000000 );
+
+	/*	On-Die Termination for Bank 3	*/
+	mtdcr( 0x10, 0x00000025 );
+	if (yucca_dimms == 2)
+		mtdcr( 0x11, 0x01800000 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x11, 0x00000000 );
+
+	/* Refresh Time register (0x30) Refresh every 7.8125uS	*/
+	mtdcr( 0x10, 0x00000030 );
+	mtdcr( 0x11, 0x08200000 );
+
+	/* SET MCIF0_MMODE  	 CL 4	*/
+	mtdcr( 0x10, 0x00000088 );
+	mtdcr( 0x11, 0x00000642 );
+
+	/* MCIF0_MEMODE	*/
+	mtdcr( 0x10, 0x00000089 );
+	mtdcr( 0x11, 0x00000004 );
+
+	/*SET MCIF0_MB0CF 	*/
+	mtdcr( 0x10, 0x00000040 );
+	mtdcr( 0x11, 0x00000201 );
+
+	/* SET MCIF0_MB1CF 	*/
+	mtdcr( 0x10, 0x00000044 );
+	mtdcr( 0x11, 0x00000201 );
+
+	/* SET MCIF0_MB2CF 	*/
+	mtdcr( 0x10, 0x00000048 );
+	if (yucca_dimms == 2)
+		mtdcr( 0x11, 0x00000201 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x11, 0x00000000 );
+
+	/* SET MCIF0_MB3CF 	*/
+	mtdcr( 0x10, 0x0000004c );
+	if (yucca_dimms == 2)
+		mtdcr( 0x11, 0x00000201 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x11, 0x00000000 );
+
+	/* SET MCIF0_INITPLR0  # NOP		*/
+	mtdcr( 0x10, 0x00000050 );
+	mtdcr( 0x11, 0xB5380000 );
+
+	/* SET MCIF0_INITPLR1  # PRE		*/
+	mtdcr( 0x10, 0x00000051 );
+	mtdcr( 0x11, 0x82100400 );
+
+	/* SET MCIF0_INITPLR2  # EMR2		*/
+	mtdcr( 0x10, 0x00000052 );
+	mtdcr( 0x11, 0x80820000 );
+
+	/* SET MCIF0_INITPLR3  # EMR3		*/
+	mtdcr( 0x10, 0x00000053 );
+	mtdcr( 0x11, 0x80830000 );
+
+	/* SET MCIF0_INITPLR4  # EMR DLL ENABLE	*/
+	mtdcr( 0x10, 0x00000054 );
+	mtdcr( 0x11, 0x80810000 );
+
+	/* SET MCIF0_INITPLR5  # MR DLL RESET	*/
+	mtdcr( 0x10, 0x00000055 );
+	mtdcr( 0x11, 0x80800542 );
+
+	/* SET MCIF0_INITPLR6  # PRE		*/
+	mtdcr( 0x10, 0x00000056 );
+	mtdcr( 0x11, 0x82100400 );
+
+	/* SET MCIF0_INITPLR7  # Refresh	*/
+	mtdcr( 0x10, 0x00000057 );
+	mtdcr( 0x11, 0x8A080000 );
+
+	/* SET MCIF0_INITPLR8  # Refresh	*/
+	mtdcr( 0x10, 0x00000058 );
+	mtdcr( 0x11, 0x8A080000 );
+
+	/* SET MCIF0_INITPLR9  # Refresh	*/
+	mtdcr( 0x10, 0x00000059 );
+	mtdcr( 0x11, 0x8A080000 );
+
+	/* SET MCIF0_INITPLR10 # Refresh	*/
+	mtdcr( 0x10, 0x0000005A );
+	mtdcr( 0x11, 0x8A080000 );
+
+	/* SET MCIF0_INITPLR11 # MR		*/
+	mtdcr( 0x10, 0x0000005B );
+	mtdcr( 0x11, 0x80800442 );
+
+	/* SET MCIF0_INITPLR12 # EMR OCD Default*/
+	mtdcr( 0x10, 0x0000005C );
+	mtdcr( 0x11, 0x80810380 );
+
+	/* SET MCIF0_INITPLR13 # EMR OCD Exit	*/
+	mtdcr( 0x10, 0x0000005D );
+	mtdcr( 0x11, 0x80810000 );
+
+	/* 0x80: Adv Addr clock by 180 deg	*/
+	mtdcr( 0x10, 0x00000080 );
+	mtdcr( 0x11, 0x80000000 );
+
+	/* 0x21: Exit self refresh, set DC_EN	*/
+	mtdcr( 0x10, 0x00000021 );
+	mtdcr( 0x11, 0x28000000 );
+
+	/* 0x81: Write DQS Adv 90 + Fractional DQS Delay	*/
+	mtdcr( 0x10, 0x00000081 );
+	mtdcr( 0x11, 0x80000800 );
+
+	/* MCIF0_SDTR1	*/
+	mtdcr( 0x10, 0x00000085 );
+	mtdcr( 0x11, 0x80201000 );
+
+	/* MCIF0_SDTR2	*/
+	mtdcr( 0x10, 0x00000086 );
+	mtdcr( 0x11, 0x42103242 );
+
+	/* MCIF0_SDTR3	*/
+	mtdcr( 0x10, 0x00000087 );
+	mtdcr( 0x11, 0x0C100D14 );
+
+	/* SET MQ0_B0BAS  base addr 00000000 / 256MB	*/
+	mtdcr( 0x40, 0x0000F800 );
+
+	/* SET MQ0_B1BAS  base addr 10000000 / 256MB	*/
+	mtdcr( 0x41, 0x0400F800 );
+
+	/* SET MQ0_B2BAS  base addr 20000000 / 256MB	*/
+	if (yucca_dimms == 2)
+		mtdcr( 0x42, 0x0800F800 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x42, 0x00000000 );
+
+	/* SET MQ0_B3BAS  base addr 30000000 / 256MB	*/
+	if (yucca_dimms == 2)
+		mtdcr( 0x43, 0x0C00F800 );
+	else if (yucca_dimms == 1)
+		mtdcr( 0x43, 0x00000000 );
+
+	/* SDRAM_RQDC	*/
+	mtdcr( 0x10, 0x00000070 );
+	mtdcr( 0x11, 0x8000003F );
+
+	/* SDRAM_RDCC	*/
+	mtdcr( 0x10, 0x00000078 );
+	mtdcr( 0x11, 0x80000000 );
+
+	/* SDRAM_RFDC	*/
+	mtdcr( 0x10, 0x00000074 );
+	mtdcr( 0x11, 0x00000220 );
+
+	return (yucca_dimms * 512) << 20;
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+	dram_size = fixed_sdram();
+
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*-------------------------------------------------------------------+
+	 *	The yucca board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *-------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	return 1;
+}
+#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*-------------------------------------------------------------------+
+	 * Disable everything
+	 *-------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*-------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+	 * strapping options to not support sizes such as 128/256 MB.
+	 *-------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIX0_BAR0, 0 );
+
+	/*-------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *-------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The yucca board is always configured as host. */
+	return 1;
+}
+#endif	/* defined(CONFIG_PCI) */
+
+int misc_init_f (void)
+{
+	uint reg;
+#if defined(CONFIG_STRESS)
+	uint i ;
+	uint disp;
+#endif
+
+	out16(FPGA_REG10, (in16(FPGA_REG10) &
+			~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
+				FPGA_REG10_10MHZ_ENABLE |
+				FPGA_REG10_100MHZ_ENABLE |
+				FPGA_REG10_GIGABIT_ENABLE |
+				FPGA_REG10_FULL_DUPLEX );
+
+	udelay(10000);	/* wait 10ms */
+
+	out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
+
+	/* minimal init for PCIe */
+	/* pci express 0 Endpoint Mode */
+	mfsdr(SDR0_PE0DLPSET, reg);
+	reg &= (~0x00400000);
+	mtsdr(SDR0_PE0DLPSET, reg);
+	/* pci express 1 Rootpoint  Mode */
+	mfsdr(SDR0_PE1DLPSET, reg);
+	reg |= 0x00400000;
+	mtsdr(SDR0_PE1DLPSET, reg);
+	/* pci express 2 Rootpoint  Mode */
+	mfsdr(SDR0_PE2DLPSET, reg);
+	reg |= 0x00400000;
+	mtsdr(SDR0_PE2DLPSET, reg);
+
+	out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
+				~FPGA_REG1C_PE0_ROOTPOINT &
+				~FPGA_REG1C_PE1_ENDPOINT  &
+				~FPGA_REG1C_PE2_ENDPOINT));
+
+#if defined(CONFIG_STRESS)
+	/*
+	 * all this setting done by linux only needed by stress an charac. test
+	 * procedure
+	 * PCIe 1 Rootpoint PCIe2 Endpoint
+	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
+	 * Power Level
+	 */
+	for (i = 0, disp = 0; i < 8; i++, disp += 3) {
+		mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
+		reg |= 0x33000000;
+		mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
+	}
+
+	/*
+	 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
+	 * Power Level
+	 */
+	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
+		mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
+		reg |= 0x33000000;
+		mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
+	}
+
+	/*
+	 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
+	 * Power Level
+	 */
+	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
+		mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
+		reg |= 0x33000000;
+		mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
+	}
+
+	reg = 0x21242222;
+	mtsdr(SDR0_PE2UTLSET1, reg);
+	reg = 0x11000000;
+	mtsdr(SDR0_PE2UTLSET2, reg);
+	/* pci express 1 Endpoint  Mode */
+	reg = 0x00004000;
+	mtsdr(SDR0_PE2DLPSET, reg);
+
+	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
+#endif
+	return 0;
+}
+
+void fpga_init(void)
+{
+	/*
+	 * by default sdram access is disabled by fpga
+	 */
+	out16(FPGA_REG10, (in16 (FPGA_REG10) |
+				FPGA_REG10_SDRAM_ENABLE |
+				FPGA_REG10_ENABLE_DISPLAY ));
+
+	return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return (ctrlc());
+}
+#endif
+
+/*---------------------------------------------------------------------------+
+ | onboard_pci_arbiter_selected => from EPLD
+ +---------------------------------------------------------------------------*/
+int onboard_pci_arbiter_selected(int core_pci)
+{
+#if 0
+	unsigned long onboard_pci_arbiter_sel;
+
+	onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
+
+	if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
+		return (BOARD_OPTION_SELECTED);
+	else
+#endif
+	return (BOARD_OPTION_NOT_SELECTED);
+}
+
+/*---------------------------------------------------------------------------+
+ | ppcMfcpr.
+ +---------------------------------------------------------------------------*/
+unsigned long ppcMfcpr(unsigned long cpr_reg)
+{
+	unsigned long msr;
+	unsigned long cpr_cfgaddr_temp;
+	unsigned long cpr_value;
+
+	msr = (mfmsr () & ~(MSR_EE));
+	cpr_cfgaddr_temp =  mfdcr(CPR0_CFGADDR);
+	mtdcr(CPR0_CFGADDR, cpr_reg);
+	cpr_value =  mfdcr(CPR0_CFGDATA);
+	mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
+	mtmsr(msr);
+
+	return (cpr_value);
+}
+
+/*----------------------------------------------------------------------------+
+| Indirect Access of the System DCR's (SDR)
+| ppcMfsdr
++----------------------------------------------------------------------------*/
+unsigned long ppcMfsdr(unsigned long sdr_reg)
+{
+	unsigned long msr;
+	unsigned long sdr_cfgaddr_temp;
+	unsigned long sdr_value;
+
+	msr = (mfmsr () & ~(MSR_EE));
+	sdr_cfgaddr_temp =  mfdcr(SDR0_CFGADDR);
+	mtdcr(SDR0_CFGADDR, sdr_reg);
+	sdr_value =  mfdcr(SDR0_CFGDATA);
+	mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
+	mtmsr(msr);
+
+	return (sdr_value);
+}
diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h
new file mode 100644
index 0000000..66f7584
--- /dev/null
+++ b/board/amcc/yucca/yucca.h
@@ -0,0 +1,363 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __YUCCA_H_
+#define __YUCCA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+
+#define TMR_FREQ_EXT		25000000
+#define BOARD_UART_CLOCK	11059200
+
+#define BOARD_OPTION_SELECTED		1
+#define BOARD_OPTION_NOT_SELECTED	0
+
+#define ENGINEERING_CLOCK_CHECKING "clk_chk"
+#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
+
+#define ENGINEERING_CLOCK_CHECKING_DATA	1
+#define ENGINEERING_EXTERNAL_CLOCK_DATA	2
+
+/* ethernet definition */
+#define MAX_ENETMODE_PARM	3
+#define ENETMODE_NEG		0
+#define ENETMODE_SPEED		1
+#define ENETMODE_DUPLEX		2
+
+#define ENETMODE_AUTONEG	0
+#define ENETMODE_NO_AUTONEG	1
+#define ENETMODE_10		2
+#define ENETMODE_100		3
+#define ENETMODE_1000		4
+#define ENETMODE_HALF		5
+#define ENETMODE_FULL		6
+
+#define NUM_TLB_ENTRIES          64
+
+/*----------------------------------------------------------------------------+
+| TLB specific defines.
++----------------------------------------------------------------------------*/
+#define TLB_256MB_ALIGN_MASK	0xF0000000
+#define TLB_16MB_ALIGN_MASK	0xFF000000
+#define TLB_1MB_ALIGN_MASK	0xFFF00000
+#define TLB_256KB_ALIGN_MASK	0xFFFC0000
+#define TLB_64KB_ALIGN_MASK	0xFFFF0000
+#define TLB_16KB_ALIGN_MASK	0xFFFFC000
+#define TLB_4KB_ALIGN_MASK	0xFFFFF000
+#define TLB_1KB_ALIGN_MASK	0xFFFFFC00
+#define TLB_256MB_SIZE		0x10000000
+#define TLB_16MB_SIZE		0x01000000
+#define TLB_1MB_SIZE		0x00100000
+#define TLB_256KB_SIZE		0x00040000
+#define TLB_64KB_SIZE		0x00010000
+#define TLB_16KB_SIZE		0x00004000
+#define TLB_4KB_SIZE		0x00001000
+#define TLB_1KB_SIZE		0x00000400
+
+#define TLB_WORD0_EPN_MASK	0xFFFFFC00
+#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_V_MASK	0x00000200
+#define TLB_WORD0_V_ENABLE	0x00000200
+#define TLB_WORD0_V_DISABLE	0x00000000
+#define TLB_WORD0_TS_MASK	0x00000100
+#define TLB_WORD0_TS_1		0x00000100
+#define TLB_WORD0_TS_0		0x00000000
+#define TLB_WORD0_SIZE_MASK	0x000000F0
+#define TLB_WORD0_SIZE_1KB	0x00000000
+#define TLB_WORD0_SIZE_4KB	0x00000010
+#define TLB_WORD0_SIZE_16KB	0x00000020
+#define TLB_WORD0_SIZE_64KB	0x00000030
+#define TLB_WORD0_SIZE_256KB	0x00000040
+#define TLB_WORD0_SIZE_1MB	0x00000050
+#define TLB_WORD0_SIZE_16MB	0x00000070
+#define TLB_WORD0_SIZE_256MB	0x00000090
+#define TLB_WORD0_TPAR_MASK	0x0000000F
+#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD1_RPN_MASK	0xFFFFFC00
+#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_PAR1_MASK	0x00000300
+#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+#define TLB_WORD1_PAR1_0	0x00000000
+#define TLB_WORD1_PAR1_1	0x00000100
+#define TLB_WORD1_PAR1_2	0x00000200
+#define TLB_WORD1_PAR1_3	0x00000300
+#define TLB_WORD1_ERPN_MASK	0x0000000F
+#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD2_PAR2_MASK	0xC0000000
+#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
+#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
+#define TLB_WORD2_PAR2_0	0x00000000
+#define TLB_WORD2_PAR2_1	0x40000000
+#define TLB_WORD2_PAR2_2	0x80000000
+#define TLB_WORD2_PAR2_3	0xC0000000
+#define TLB_WORD2_U0_MASK	0x00008000
+#define TLB_WORD2_U0_ENABLE	0x00008000
+#define TLB_WORD2_U0_DISABLE	0x00000000
+#define TLB_WORD2_U1_MASK	0x00004000
+#define TLB_WORD2_U1_ENABLE	0x00004000
+#define TLB_WORD2_U1_DISABLE	0x00000000
+#define TLB_WORD2_U2_MASK	0x00002000
+#define TLB_WORD2_U2_ENABLE	0x00002000
+#define TLB_WORD2_U2_DISABLE	0x00000000
+#define TLB_WORD2_U3_MASK	0x00001000
+#define TLB_WORD2_U3_ENABLE	0x00001000
+#define TLB_WORD2_U3_DISABLE	0x00000000
+#define TLB_WORD2_W_MASK	0x00000800
+#define TLB_WORD2_W_ENABLE	0x00000800
+#define TLB_WORD2_W_DISABLE	0x00000000
+#define TLB_WORD2_I_MASK	0x00000400
+#define TLB_WORD2_I_ENABLE	0x00000400
+#define TLB_WORD2_I_DISABLE	0x00000000
+#define TLB_WORD2_M_MASK	0x00000200
+#define TLB_WORD2_M_ENABLE	0x00000200
+#define TLB_WORD2_M_DISABLE	0x00000000
+#define TLB_WORD2_G_MASK	0x00000100
+#define TLB_WORD2_G_ENABLE	0x00000100
+#define TLB_WORD2_G_DISABLE	0x00000000
+#define TLB_WORD2_E_MASK	0x00000080
+#define TLB_WORD2_E_ENABLE	0x00000080
+#define TLB_WORD2_E_DISABLE	0x00000000
+#define TLB_WORD2_UX_MASK	0x00000020
+#define TLB_WORD2_UX_ENABLE	0x00000020
+#define TLB_WORD2_UX_DISABLE	0x00000000
+#define TLB_WORD2_UW_MASK	0x00000010
+#define TLB_WORD2_UW_ENABLE	0x00000010
+#define TLB_WORD2_UW_DISABLE	0x00000000
+#define TLB_WORD2_UR_MASK	0x00000008
+#define TLB_WORD2_UR_ENABLE	0x00000008
+#define TLB_WORD2_UR_DISABLE	0x00000000
+#define TLB_WORD2_SX_MASK	0x00000004
+#define TLB_WORD2_SX_ENABLE	0x00000004
+#define TLB_WORD2_SX_DISABLE	0x00000000
+#define TLB_WORD2_SW_MASK	0x00000002
+#define TLB_WORD2_SW_ENABLE	0x00000002
+#define TLB_WORD2_SW_DISABLE	0x00000000
+#define TLB_WORD2_SR_MASK	0x00000001
+#define TLB_WORD2_SR_ENABLE	0x00000001
+#define TLB_WORD2_SR_DISABLE	0x00000000
+
+/*----------------------------------------------------------------------------+
+| Board specific defines.
++----------------------------------------------------------------------------*/
+#define NONCACHE_MEMORY_SIZE     (64*1024)
+#define NONCACHE_AREA0_ENDOFFSET (64*1024)
+#define NONCACHE_AREA1_ENDOFFSET (32*1024)
+
+#define FLASH_SECTORSIZE	0x00010000
+
+/* SDRAM MICRON */
+#define SDRAM_MICRON		0x2C
+
+#define SDRAM_TRUE		1
+#define SDRAM_FALSE		0
+#define SDRAM_DDR1		1
+#define SDRAM_DDR2		2
+#define SDRAM_NONE		0
+#define MAXDIMMS		2		/* Changes le 12/01/05 pour 1.6 */
+#define MAXRANKS		4		/* Changes le 12/01/05 pour 1.6 */
+#define MAXBANKSPERDIMM		2
+#define MAXRANKSPERDIMM		2
+#define MAXBXCF			4		/* Changes le 12/01/05 pour 1.6 */
+#define MAXSDRAMMEMORY		0xFFFFFFFF	/* 4GB */
+#define ERROR_STR_LENGTH	256
+#define MAX_SPD_BYTES		256		/* Max number of bytes on the DIMM's SPD EEPROM */
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+/* Serial Device Strap Reg 0 */
+#define sdr_pstrp0	0x0040
+
+#define	SDR0_SDSTP1_EBC_ROM_BS_MASK	0x00000080 /* EBC Boot bus width Mask */
+#define	SDR0_SDSTP1_EBC_ROM_BS_16BIT	0x00000080 /* EBC 16 Bits */
+#define	SDR0_SDSTP1_EBC_ROM_BS_8BIT	0x00000000 /* EBC  8 Bits */
+
+#define	SDR0_SDSTP1_BOOT_SEL_MASK	0x00080000 /* Boot device Selection Mask */
+#define	SDR0_SDSTP1_BOOT_SEL_EBC	0x00000000 /* EBC */
+#define	SDR0_SDSTP1_BOOT_SEL_PCI	0x00080000 /* PCI */
+
+#define	SDR0_SDSTP1_EBC_SIZE_MASK	0x00000060 /* Boot rom size Mask */
+#define	SDR0_SDSTP1_BOOT_SIZE_16MB	0x00000060 /* 16 MB */
+#define	SDR0_SDSTP1_BOOT_SIZE_8MB	0x00000040 /*  8 MB */
+#define	SDR0_SDSTP1_BOOT_SIZE_4MB	0x00000020 /*  4 MB */
+#define	SDR0_SDSTP1_BOOT_SIZE_2MB	0x00000000 /*  2 MB */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0			0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000  /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000  /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000  /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000  /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000  /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000  /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000  /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000  /* Default strap settings 7 */
+
+/* fpgareg - defines are in include/config/YUCCA.h */
+
+#define SDR0_CUST0_ENET3_MASK		0x00000080
+#define SDR0_CUST0_ENET3_COPPER		0x00000000
+#define SDR0_CUST0_ENET3_FIBER		0x00000080
+#define SDR0_CUST0_RGMII3_MASK		0x00000070
+#define SDR0_CUST0_RGMII3_ENCODE(n)	((((unsigned long)(n))&0x7)<<4)
+#define SDR0_CUST0_RGMII3_DECODE(n)	((((unsigned long)(n))>>4)&0x07)
+#define SDR0_CUST0_RGMII3_DISAB		0x00000000
+#define SDR0_CUST0_RGMII3_RTBI		0x00000040
+#define SDR0_CUST0_RGMII3_RGMII		0x00000050
+#define SDR0_CUST0_RGMII3_TBI		0x00000060
+#define SDR0_CUST0_RGMII3_GMII		0x00000070
+#define SDR0_CUST0_ENET2_MASK		0x00000008
+#define SDR0_CUST0_ENET2_COPPER		0x00000000
+#define SDR0_CUST0_ENET2_FIBER		0x00000008
+#define SDR0_CUST0_RGMII2_MASK		0x00000007
+#define SDR0_CUST0_RGMII2_ENCODE(n)	((((unsigned long)(n))&0x7)<<0)
+#define SDR0_CUST0_RGMII2_DECODE(n)	((((unsigned long)(n))>>0)&0x07)
+#define SDR0_CUST0_RGMII2_DISAB		0x00000000
+#define SDR0_CUST0_RGMII2_RTBI		0x00000004
+#define SDR0_CUST0_RGMII2_RGMII		0x00000005
+#define SDR0_CUST0_RGMII2_TBI		0x00000006
+#define SDR0_CUST0_RGMII2_GMII		0x00000007
+
+#define ONE_MILLION			1000000
+#define ONE_BILLION			1000000000
+
+/*----------------------------------------------------------------------------+
+|                               X
+|                              XX
+| XX  XXX   XXXXX   XX XXX    XXXXX
+| XX  XX        X    XXX XX    XX
+| XX  XX   XXXXXX    XX        XX
+| XX  XX   X   XX    XX        XX XX
+|  XXX XX  XXXXX X  XXXX        XXX
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+| Declare Configuration values
++----------------------------------------------------------------------------*/
+
+typedef enum config_selection {
+	CONFIG_NOT_SELECTED,
+	CONFIG_SELECTED
+} config_selection_t;
+
+typedef enum config_list {
+	UART2_IN_SERVICE_MODE,
+	CPU_TRACE_MODE,
+	UART1_CTS_RTS,
+	CONFIG_NB
+} config_list_t;
+
+#define MAX_CONFIG_SELECT_NB			3
+
+#define BOARD_INFO_UART2_IN_SERVICE_MODE	1
+#define BOARD_INFO_CPU_TRACE_MODE		2
+#define BOARD_INFO_UART1_CTS_RTS_MODE		4
+
+void force_bup_config_selection(config_selection_t *confgi_select_P);
+void update_config_selection_table(config_selection_t *config_select_P);
+void display_config_selection(config_selection_t *config_select_P);
+
+/*----------------------------------------------------------------------------+
+|                     XX
+|
+|   XXXX    XX XXX   XXX     XXXX
+|  XX        XX  XX   XX    XX  XX
+|  XX  XXX   XX  XX   XX    XX  XX
+|  XX  XX    XXXXX    XX    XX  XX
+|   XXXX     XX      XXXX    XXXX
+|           XXXX
+|
+|
+|
+| +------------------------------------------------------------------+
+| |  GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
+| +----------------------+------------------+-----+------------+-----+
+| |                      |                  |     |            |     |
+| | GPIO0_0              | PCIX0REQ2_N      | I/O |  TRCCLK    |     |
+| | GPIO0_1              | PCIX0REQ3_N      | I/O |  TRCBS0    |     |
+| | GPIO0_2              | PCIX0GNT2_N      | I/O |  TRCBS1    |     |
+| | GPIO0_3              | PCIX0GNT3_N      | I/O |  TRCBS2    |     |
+| | GPIO0_4              | PCIX1REQ2_N      | I/O |  TRCES0    |     |
+| | GPIO0_5              | PCIX1REQ3_N      | I/O |  TRCES1    |     |
+| | GPIO0_6              | PCIX1GNT2_N      | I/O |  TRCES2    | NA  |
+| | GPIO0_7              | PCIX1GNT3_N      | I/O |  TRCES3    | NA  |
+| | GPIO0_8              | PERREADY         |  I  |  TRCES4    | NA  |
+| | GPIO0_9              | PERCS1_N         |  O  |  TRCTS0    | NA  |
+| | GPIO0_10             | PERCS2_N         |  O  |  TRCTS1    | NA  |
+| | GPIO0_11             | IRQ0             |  I  |  TRCTS2    | NA  |
+| | GPIO0_12             | IRQ1             |  I  |  TRCTS3    | NA  |
+| | GPIO0_13             | IRQ2             |  I  |  TRCTS4    | NA  |
+| | GPIO0_14             | IRQ3             |  I  |  TRCTS5    | NA  |
+| | GPIO0_15             | IRQ4             |  I  |  TRCTS6    | NA  |
+| | GPIO0_16             | IRQ5             |  I  |  UART2RX   |  I  |
+| | GPIO0_17             | PERBE0_N         |  O  |  UART2TX   |  O  |
+| | GPIO0_18             | PCI0GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_19             | PCI0GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_20             | PCI0REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_21             | PCI0REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_22             | PCI1GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_23             | PCI1GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_24             | PCI1REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_25             | PCI1REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_26             | PCI2GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_27             | PCI2GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_28             | PCI2REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_29             | PCI2REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_30             | UART1RX          |  I  |  NA        | NA  |
+| | GPIO0_31             | UART1TX          |  O  |  NA        | NA  |
+| |                      |                  |     |            |     |
+| +----------------------+------------------+-----+------------+-----+
+|
++----------------------------------------------------------------------------*/
+
+unsigned long auto_calc_speed(void);
+/*----------------------------------------------------------------------------+
+| Prototypes
++----------------------------------------------------------------------------*/
+void print_evb440spe_info(void);
+
+int onboard_pci_arbiter_selected(int core_pci);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __YUCCA_H_ */