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authorStefan Roese <sr@denx.de>2007-05-05 08:29:01 +0200
committerStefan Roese <sr@denx.de>2007-05-05 08:29:01 +0200
commitf544ff6656fca263ed1ebe39899b6d95da67c8b8 (patch)
tree32d746347699bc9e4c1353c1d605d86d35ae9057 /board/amcc
parentbd38b7ecfdf01e0b7bce551a0834226630be81c1 (diff)
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ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc')
-rw-r--r--board/amcc/sequoia/sdram.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index f8b837e..d045df1 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
}
#endif /* CONFIG_DDR_DATA_EYE */
+#if defined(CONFIG_NAND_SPL)
+/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val) 133000000
+#endif
+
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@@ -404,7 +412,7 @@ long int initdram (int board_type)
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
- if (speed > 133333333)
+ if (speed > 133333334)
mtsdram(DDR0_26, 0x5B26050C);
else
mtsdram(DDR0_26, 0x5B260408);