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authorLarry Johnson <lrj@arlinx.com>2007-12-22 15:34:39 -0500
committerStefan Roese <sr@denx.de>2007-12-27 19:35:35 +0100
commitd3471173e14b7544bb60339eda8d3d3906694b0a (patch)
treea4b5f40f98bdb9060e560ec9809a9febceafe33e /board/amcc
parentc68f59fe3ec16769f82b5fca7421983c336d3aac (diff)
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Use out_be32() and friends to access memory-mapped registers in sequoia.c
Signed-off-by: Larry Johnson <lrj@acm.org>
Diffstat (limited to 'board/amcc')
-rw-r--r--board/amcc/sequoia/sequoia.c58
1 files changed, 29 insertions, 29 deletions
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index f81f071..37b4f31 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -48,31 +48,31 @@ int board_early_init_f(void)
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/* test-only: take GPIO init from pcs440ep ???? in config file */
- out32(GPIO0_OR, 0x00000000);
- out32(GPIO0_TCR, 0x0000000f);
- out32(GPIO0_OSRL, 0x50015400);
- out32(GPIO0_OSRH, 0x550050aa);
- out32(GPIO0_TSRL, 0x50015400);
- out32(GPIO0_TSRH, 0x55005000);
- out32(GPIO0_ISR1L, 0x50000000);
- out32(GPIO0_ISR1H, 0x00000000);
- out32(GPIO0_ISR2L, 0x00000000);
- out32(GPIO0_ISR2H, 0x00000100);
- out32(GPIO0_ISR3L, 0x00000000);
- out32(GPIO0_ISR3H, 0x00000000);
-
- out32(GPIO1_OR, 0x00000000);
- out32(GPIO1_TCR, 0xc2000000);
- out32(GPIO1_OSRL, 0x5c280000);
- out32(GPIO1_OSRH, 0x00000000);
- out32(GPIO1_TSRL, 0x0c000000);
- out32(GPIO1_TSRH, 0x00000000);
- out32(GPIO1_ISR1L, 0x00005550);
- out32(GPIO1_ISR1H, 0x00000000);
- out32(GPIO1_ISR2L, 0x00050000);
- out32(GPIO1_ISR2H, 0x00000000);
- out32(GPIO1_ISR3L, 0x01400000);
- out32(GPIO1_ISR3H, 0x00000000);
+ out_be32((u32 *) GPIO0_OR, 0x00000000);
+ out_be32((u32 *) GPIO0_TCR, 0x0000000f);
+ out_be32((u32 *) GPIO0_OSRL, 0x50015400);
+ out_be32((u32 *) GPIO0_OSRH, 0x550050aa);
+ out_be32((u32 *) GPIO0_TSRL, 0x50015400);
+ out_be32((u32 *) GPIO0_TSRH, 0x55005000);
+ out_be32((u32 *) GPIO0_ISR1L, 0x50000000);
+ out_be32((u32 *) GPIO0_ISR1H, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR2H, 0x00000100);
+ out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
+
+ out_be32((u32 *) GPIO1_OR, 0x00000000);
+ out_be32((u32 *) GPIO1_TCR, 0xc2000000);
+ out_be32((u32 *) GPIO1_OSRL, 0x5c280000);
+ out_be32((u32 *) GPIO1_OSRH, 0x00000000);
+ out_be32((u32 *) GPIO1_TSRL, 0x0c000000);
+ out_be32((u32 *) GPIO1_TSRH, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR1L, 0x00005550);
+ out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR2L, 0x00050000);
+ out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR3L, 0x01400000);
+ out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@@ -102,16 +102,16 @@ int board_early_init_f(void)
mtdcr(uic2sr, 0xffffffff); /* clear all */
/* 50MHz tmrclk */
- *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+ out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
/* clear write protects */
- *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+ out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
/* enable Ethernet */
- *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
+ out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
/* enable USB device */
- *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
+ out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);