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| author | Stefan Roese <sr@denx.de> | 2006-07-28 18:34:58 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2006-07-28 18:34:58 +0200 |
| commit | a2c95a72247990dee9a03b26b4dc9fc0182c97ed (patch) | |
| tree | cabdaa860480f895cccc6600f3454a751329c13c /board/amcc | |
| parent | fc6c4a67ae94adac02da6257a0f5adc3bd48ebec (diff) | |
| download | u-boot-imx-a2c95a72247990dee9a03b26b4dc9fc0182c97ed.zip u-boot-imx-a2c95a72247990dee9a03b26b4dc9fc0182c97ed.tar.gz u-boot-imx-a2c95a72247990dee9a03b26b4dc9fc0182c97ed.tar.bz2 | |
PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
Diffstat (limited to 'board/amcc')
| -rw-r--r-- | board/amcc/yellowstone/yellowstone.c | 4 | ||||
| -rw-r--r-- | board/amcc/yosemite/yosemite.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c index 86d0db7..92dc9d4 100644 --- a/board/amcc/yellowstone/yellowstone.c +++ b/board/amcc/yellowstone/yellowstone.c @@ -313,13 +313,13 @@ void sdram_init(void) mtsdram(mem_tr0, 0x410a4012); /* ?? */ mtsdram(mem_rtr, 0x04080000); /* ?? */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ + mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram(mem_cfg0, 0x84000000); /* Enable */ + mtsdram(mem_cfg0, 0x80000000); /* Enable */ for (;;) { mfsdram(mem_mcsts, reg); diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 6742441..7f2e718 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -309,13 +309,13 @@ void sdram_init(void) mtsdram(mem_tr0, 0x410a4012); /* ?? */ mtsdram(mem_rtr, 0x04080000); /* ?? */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ + mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram(mem_cfg0, 0x84000000); /* Enable */ + mtsdram(mem_cfg0, 0x80000000); /* Enable */ for (;;) { mfsdram(mem_mcsts, reg); |