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| author | Stefan Roese <sr@denx.de> | 2005-11-03 08:31:33 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2005-11-03 08:31:33 +0100 |
| commit | ef04a0aa2676738847bd69914cadac0b96d6e731 (patch) | |
| tree | 4de5b484f76178f632e080bd9ed1c522c9f6f7f1 /board/amcc/yosemite | |
| parent | 57275b69c6cdb5ed37c4cdece3cda56487ca4b0c (diff) | |
| download | u-boot-imx-ef04a0aa2676738847bd69914cadac0b96d6e731.zip u-boot-imx-ef04a0aa2676738847bd69914cadac0b96d6e731.tar.gz u-boot-imx-ef04a0aa2676738847bd69914cadac0b96d6e731.tar.bz2 | |
Additional fix for external IRQ config on Yellowstone & Yosemite
Patch by Stefan Roese, 03 Nov 2005
Diffstat (limited to 'board/amcc/yosemite')
| -rw-r--r-- | board/amcc/yosemite/yosemite.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 03b412b..bc3d85b 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -56,25 +56,6 @@ int board_early_init_f(void) mtebc(pb5cr, 0x00000000); /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- * Setup the GPIO pins *-------------------------------------------------------------------*/ /*CPLD cs */ @@ -108,6 +89,25 @@ int board_early_init_f(void) out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- * Setup other serial configuration *-------------------------------------------------------------------*/ mfsdr(sdr_pci0, reg); |