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| author | Stefan Roese <sr@denx.de> | 2005-09-15 11:34:07 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2005-09-15 11:34:07 +0200 |
| commit | 34c0a5e98badc0aa313a2563f9c1df79632b8265 (patch) | |
| tree | 2911cdfbb70bad51611805835f21e486a08650c1 /board/amcc/yellowstone/init.S | |
| parent | 3edb0ccf61ab495edf400f8baf1a2d333ae2fe1c (diff) | |
| download | u-boot-imx-34c0a5e98badc0aa313a2563f9c1df79632b8265.zip u-boot-imx-34c0a5e98badc0aa313a2563f9c1df79632b8265.tar.gz u-boot-imx-34c0a5e98badc0aa313a2563f9c1df79632b8265.tar.bz2 | |
Update AMCC Yosemite to get a consistent setup for all AMCC eval
boards (baudrate, environment...). Flash driver fixed.
Patch by Stefan Roese, 15 Sep 2005
Diffstat (limited to 'board/amcc/yellowstone/init.S')
| -rw-r--r-- | board/amcc/yellowstone/init.S | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/board/amcc/yellowstone/init.S b/board/amcc/yellowstone/init.S index 7ba43c7..425ad08 100644 --- a/board/amcc/yellowstone/init.S +++ b/board/amcc/yellowstone/init.S @@ -86,14 +86,19 @@ tlbtab: tlbtab_start - /* - 0xf0000000 must be first, before relocation SA_I must be off to use the - dcache as stack. It is patched after relocation to enable SA_I - */ - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) /* PCI */ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) |