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authorStefan Roese <sr@denx.de>2007-10-17 15:40:19 +0200
committerStefan Roese <sr@denx.de>2007-10-18 07:44:56 +0200
commit3e11ae80fec1ee12194940955431186abf6009c2 (patch)
tree2ce8fcd20ada58b28c9c0935dea9a436846dd77b /board/amcc/sequoia
parenteff786a9b89144478f478c4193fcad5b498feb72 (diff)
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ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/sequoia')
-rw-r--r--board/amcc/sequoia/cmd_sequoia.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
index e7997e9..6b9043a 100644
--- a/board/amcc/sequoia/cmd_sequoia.c
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -40,7 +40,7 @@
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
- * the only value affected for a 66MHz PCI and simply needs a +0x10.
+ * the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
@@ -57,6 +57,7 @@ static char *config_labels[] = {
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
@@ -98,6 +99,11 @@ static u8 boot_configs[][17] = {
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
+ (NOR_COMPATIBLE),
+ 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00