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| author | Stefan Roese <sr@denx.de> | 2010-04-14 13:57:18 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-04-19 15:29:03 +0200 |
| commit | cf6eb6da433179674571f9370566b1ec8989a41a (patch) | |
| tree | fc0ad7161d7146154026fa789a97dd2c047c61a7 /board/amcc/sequoia | |
| parent | 2a72e9ed18d2164eb7fe569119342eb631b568da (diff) | |
| download | u-boot-imx-cf6eb6da433179674571f9370566b1ec8989a41a.zip u-boot-imx-cf6eb6da433179674571f9370566b1ec8989a41a.tar.gz u-boot-imx-cf6eb6da433179674571f9370566b1ec8989a41a.tar.bz2 | |
ppc4xx: TLB init file cleanup
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.
Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/sequoia')
| -rw-r--r-- | board/amcc/sequoia/init.S | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index f090070..7139aae 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -41,7 +41,7 @@ tlbtab: tlbtab_start /* vxWorks needs this as first entry for the Machine Check interrupt */ - tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) /* * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This @@ -51,49 +51,49 @@ tlbtab: #ifndef CONFIG_SYS_RAMBOOT /* TLB-entry for DDR SDRAM (Up to 2GB) */ #ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G) #else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) #endif #endif /* CONFIG_SYS_RAMBOOT */ /* TLB-entry for EBC */ - tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG ) /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ #ifndef CONFIG_NAND_SPL - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) #else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) #endif #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) /* TLB-entry for NAND */ - tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) /* TLB-entry for Internal Registers & OCM */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) + tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) /* TLB-entry PCI IO Space - from sr@denx.de */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) tlbtab_end @@ -104,7 +104,7 @@ tlbtab: */ #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) +#define TLB02 TLB2(AC_RWX | SA_IG) .globl reconfig_tlb0 reconfig_tlb0: |