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authorNobuhiro Iwamatsu <iwamatsu@nigauri.org>2007-11-29 00:56:37 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2007-11-29 00:56:37 +0900
commit7fc792895be3c0edf423c4038992b40345672a12 (patch)
tree6247dce2d1e72aa17fd2d7a138af66158d02f319 /board/amcc/sequoia
parenteda3e1e6619ad0bee94ae4b16c99d88e77e2af13 (diff)
parentf92edbd8a0ef16a2b9127cbb564c09685728e4b0 (diff)
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u-boot-imx-7fc792895be3c0edf423c4038992b40345672a12.tar.gz
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Merge git://www.denx.de/git/u-boot
Conflicts: drivers/Makefile
Diffstat (limited to 'board/amcc/sequoia')
-rw-r--r--board/amcc/sequoia/cmd_sequoia.c17
-rw-r--r--board/amcc/sequoia/sequoia.c7
2 files changed, 18 insertions, 6 deletions
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
index f3803c0..6b9043a 100644
--- a/board/amcc/sequoia/cmd_sequoia.c
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <command.h>
#include <i2c.h>
+#include <asm/io.h>
/*
* There are 2 versions of production Sequoia & Rainier platforms.
@@ -39,7 +40,7 @@
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
- * the only value affected for a 66MHz PCI and simply needs a +0x10.
+ * the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
@@ -56,6 +57,7 @@ static char *config_labels[] = {
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
@@ -97,6 +99,11 @@ static u8 boot_configs[][17] = {
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
+ (NOR_COMPATIBLE),
+ 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
@@ -200,8 +207,12 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
/* check CPLD register +5 for PCI 66MHz flag */
- if (in8(CFG_BCSR_BASE + 5) & 0x01)
- buf[5] += 0x10;
+ if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
+ /*
+ * PLB-to-PCI divisor = 3 for 33MHz sync PCI
+ * instead of 2 for 66MHz systems
+ */
+ buf[5] |= 0x08;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index f823117..4e47ab3 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@@ -24,6 +24,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <ppc440.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -362,8 +363,8 @@ int checkboard(void)
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
- rev = in8(CFG_BCSR_BASE + 0);
- val = in8(CFG_BCSR_BASE + 5) & 0x01;
+ rev = in_8((void *)(CFG_BCSR_BASE + 0));
+ val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {