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| author | Niklaus Giger <niklaus.giger@member.fsf.org> | 2009-10-04 20:04:20 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-07 09:15:20 +0200 |
| commit | ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd (patch) | |
| tree | 5c390395480e4cfd575ef751edd34034eaffa142 /board/amcc/sequoia | |
| parent | f80e61dcfe53fa3a5936659883415c9bd1b5a3d9 (diff) | |
| download | u-boot-imx-ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd.zip u-boot-imx-ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd.tar.gz u-boot-imx-ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd.tar.bz2 | |
ppc_4xx: Apply new HW register names
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/sequoia')
| -rw-r--r-- | board/amcc/sequoia/sequoia.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 17f831c..d42c802 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -428,26 +428,26 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /* * Set up Configuration registers |