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authorStefan Roese <sr@denx.de>2009-05-11 13:46:14 +0200
committerWolfgang Denk <wd@denx.de>2009-06-12 20:39:47 +0200
commitd873133f2ba9bd613d5f6552c31cc70fb13f15d3 (patch)
tree01a00655040050e5125ef15a24e01e605eb02ec6 /board/amcc/sequoia/sdram.c
parent837db3d87f4bfe9261629fb4a1bb433506a3056a (diff)
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ppc4xx: Add Sequoia RAM-booting target
This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/sequoia/sdram.c')
-rw-r--r--board/amcc/sequoia/sdram.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 6df4c6d..bde471c 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -54,7 +54,8 @@ extern void denali_core_search_data_eye(void);
************************************************************************/
phys_size_t initdram (int board_type)
{
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
+ defined(CONFIG_NAND_SPL)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);